Patents by Inventor Sandeep Gupta

Sandeep Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099602
    Abstract: A system and associated methods for accurate localization of seizure onset zone (SOZ) from independent components (IC) of resting state functional magnetic resonance imaging (rs-fMRI) to improve surgical outcomes in children with Drug Resistant Epilepsy (DRE) are disclosed. The system and methods define a phased approach, where fMRI noise-related biomarkers are used through high fidelity image processing techniques to eliminate noise ICs. Then SOZ markers are used through a maximum likelihood-based classifier to determine SOZ localizing ICs.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 28, 2024
    Applicant: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Ayan Banerjee, Sandeep Gupta, Varina Boerwinkle
  • Patent number: 11921640
    Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Vivek Venkatraman, Sandeep Gupta, Eric J. Furbish, Srinivasa Rangan Sridharan, Stephan G. Meier
  • Publication number: 20240067108
    Abstract: A method for a process of signal transmission between a plurality of electrical units, wherein the method comprises: electrically interconnecting the plurality of electrical units by way of a plurality of electrical junction blocks, each electrical junction block of the plurality of electrical junction blocks comprising one or more terminals. An arrangement for signal transmission between a plurality of electrical units, wherein the arrangement comprises a plurality of electrical junction blocks for electrically interconnecting the plurality of electrical units, and wherein each electrical junction block of the plurality of electrical junction blocks comprises one or more terminals.
    Type: Application
    Filed: February 2, 2022
    Publication date: February 29, 2024
    Applicant: Scania CV AB
    Inventor: Sandeep GUPTA
  • Patent number: 11893241
    Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: February 6, 2024
    Assignee: Apple Inc.
    Inventors: Brian P. Lilly, Sandeep Gupta, Chandan Shantharaj, Krishna C. Potnuru, Sahil Kapoor
  • Publication number: 20230418724
    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.
    Type: Application
    Filed: June 29, 2023
    Publication date: December 28, 2023
    Inventors: Andrew J. Beaumont-Smith, Sandeep Gupta, Krishna C. Potnuru, Matthias Knoth
  • Publication number: 20230385847
    Abstract: The operational characteristics of a cyber-physical system (CPS) may deviate from the certified system due to intended (in case of cheating) or unintended (wear and tear) reasons. A computer-implemented certification system makes test case search aware of the multidimensional interactions between the cyber and physical subsystems and addresses practical dynamical system problems like Zeno behavior and dynamical model divergence. The system dynamically modulates an input search space by predicting and limiting input variations that can potentially cause divergence or Zeno behavior.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 30, 2023
    Applicant: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Sandeep Gupta, Aranyak Maity, Ayan Banerjee, Imane Lamrani
  • Patent number: 11822480
    Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Vivek Venkatraman, Sandeep Gupta, Eric J. Furbish, Srinivasa Rangan Sridharan, Stephan G. Meier
  • Publication number: 20230359557
    Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Applicant: Apple Inc.
    Inventors: Sandeep Gupta, Brian P. Lilly, Krishna C. Potnuru
  • Patent number: 11783615
    Abstract: A system and associated methods/processes includes a sensor operable to capture sensor data indicative of a gesture; and a processor in communication with a memory and the sensor. The processor is configured to execute instructions stored in the memory, which, when executed, cause the processor to access the sensor data and decompose the gesture into a canonical gesture form defining a string of gesture components arranged in a spatio-temporal order.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 10, 2023
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Sandeep Gupta, Ayan Banerjee
  • Publication number: 20230270746
    Abstract: Embodiments of the disclosure relate generally to formulations, methods of treatment, kits, and dosage forms for treating inflammatory disorders, including topic dermatitis, cancer, the formulations comprising an active pharmaceutical ingredient. The formulation provided comprises granules, wherein the granules comprise: micronized active ingredient; one or more granulation binders; one or more fillers; one or more disintegrants; and one or more antioxidants. In one embodiment, the methods of treatment include orally administering the active ingredient to a subject suffering from atopic dermatitis, where the active ingredient, is in an amount of about 20 mg to about 80 mg.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 31, 2023
    Inventors: Aruna Railkar, Paras Jariwala, Wantanee Phuapradit, David Zammit, Louis Denis, Niranjan Rao, Helen Usansky, Sandeep Gupta
  • Patent number: 11741009
    Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: August 29, 2023
    Assignee: Apple Inc.
    Inventors: Sandeep Gupta, Brian P Lilly, Krishna C Potnuru
  • Patent number: 11740993
    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Apple Inc.
    Inventors: Andrew J. Beaumont-Smith, Sandeep Gupta, Krishna C. Potnuru, Matthias Knoth
  • Patent number: 11734771
    Abstract: Systems and methods for generating a custom document template are disclosed. An example method may be performed by one or more processors of a system and include retrieving a user document including a user data entry in a user data field, identifying a set of system data fields within a plurality of system documents potentially relevant to the user document, determining, for each of the set of system data fields, a weighted value indicative of a likelihood that the system data field is relevant to the user data field, identifying a most relevant system data field of the set of system data fields, the most relevant system data field having a highest weighted value of the determined weighted values, and generating a custom document template including a dynamic data region for the user data entry, the dynamic data region mapped to the most relevant system data field.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: August 22, 2023
    Assignee: Intuit Inc.
    Inventors: Bala Dutt, Rahul Vankudothu, Prabhat Hegde, Anurag Tyagi, Sunil Tandra Sishtla, Sandeep Gupta
  • Publication number: 20230254283
    Abstract: Distributed firewalls in a network are disclosed. Example firewall controllers disclosed herein are to instruct a first network node of a software-defined network to implement a first firewall instance of a distributed firewall, the first network node to implement the first firewall instance with a first virtual machine. Disclosed example firewall controllers are also to configure a second network node of the software-defined network to route network traffic through the first firewall instance and, after at least some of the network traffic is dropped by the first firewall instance, instruct the second network node to implement a second firewall instance of the distributed firewall, the second network node to implement the second firewall instance with a second virtual machine.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Dustin Grant, Sandeep Gupta, Sridhar Narahari, Michael J. Satterlee
  • Publication number: 20230214703
    Abstract: Predicting energy production for energy generating assets, including: receiving current and forecasted meteorological data associated with a location of an energy generating asset; and predicting an energy production value produced by the energy generating asset at a predetermined time based on the current and forecasted meteorological data using a trained model for the energy generating asset, the trained model being trained using a machine learning algorithm that utilizes historical meteorological data associated with the location of the energy generating asset and historical production capability data associated with a historical production capability of the energy generating asset.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventors: SAHIL MAHESWARI, SANDEEP GUPTA, JAYESH SHAH
  • Publication number: 20230213560
    Abstract: Calculating energy loss during an outage, including: determining that windspeed data indicating device windspeeds measured at an energy generating device are unavailable within a particular time duration; receiving meteorological data associated with a site location of the energy generating device, the meteorological data including meteorological windspeed data collected within the particular time duration; and predicting one or more estimated device windspeeds at the energy generating device during the particular time duration based on the meteorological data using a trained model for the energy generating device, the trained model being trained using a machine learning algorithm that utilizes historical meteorological windspeed data associated with the site location collected during a previous time duration and corresponding historical device windspeed data measured at the energy generating device during the previous time duration.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventors: SAHIL MAHESWARI, SANDEEP GUPTA, JAYESH SHAH, KATE WESSELS
  • Patent number: 11665140
    Abstract: Distributed firewalls in a network are disclosed. Example firewall controllers disclosed herein are to instruct a first network node of a software-defined network to implement a first firewall instance of a distributed firewall, the first network node to implement the first firewall instance with a first virtual machine. Disclosed example firewall controllers are also to configure a second network node of the software-defined network to route network traffic through the first firewall instance and, after at least some of the network traffic is dropped by the first firewall instance, instruct the second network node to implement a second firewall instance of the distributed firewall, the second network node to implement the second firewall instance with a second virtual machine.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 30, 2023
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Dustin Grant, Sandeep Gupta, Sridhar Narahari, Michael J. Satterlee
  • Publication number: 20230138746
    Abstract: The present disclosure discloses a data science driven system and associated methodology framework for mining relevant knowledge from input/output traces of a closed-loop control system for glycemic control to aid in actionable feedback for Type 1 diabetes management. The framework takes Continuous Glucose Monitor (CGM) records and insulin pump records from a closed loop control (CLC) system and interprets the CGM records and insulin pump data to provide medically useful information, wherein the closed-loop control system is operable for operation in an “auto mode” (AP) and a “manual mode” (SAP).
    Type: Application
    Filed: March 19, 2021
    Publication date: May 4, 2023
    Inventors: SANDEEP GUPTA, AYAN BANERJEE, YOGISH C. KUDVA
  • Publication number: 20230101696
    Abstract: A system examines components of gestures of a gesture-based language for evaluating proper execution of the gesture, and also examines components of new gestures for evaluating lexical similarity with existing gestures of similar meaning or theme.
    Type: Application
    Filed: September 30, 2022
    Publication date: March 30, 2023
    Applicant: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Ayan Banerjee, Sandeep Gupta, Sameena Hossain
  • Publication number: 20230061419
    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 2, 2023
    Inventors: Andrew J. Beaumont-Smith, Sandeep Gupta, Krishna C. Potnuru, Matthias Knoth