Patents by Inventor Sandeep Kumar Goel

Sandeep Kumar Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9390219
    Abstract: A method of detecting one or more faults in a semiconductor device that includes generating a first test pattern set from a primary node list and a fault list. The primary node list includes one or more nodes and the fault list identifies one or more faults. The method also includes generating one or more secondary node lists from the primary node list and generating a second test pattern set from at least the first test pattern set and the secondary node list. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Sandeep Kumar Goel, Yuan-Han Lee
  • Patent number: 9391110
    Abstract: A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 9341672
    Abstract: A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Saman M. I. Adham
  • Publication number: 20160133529
    Abstract: A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventor: Sandeep Kumar Goel
  • Publication number: 20160050350
    Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Ashok MEHTA
  • Publication number: 20160049435
    Abstract: A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE
  • Publication number: 20160041225
    Abstract: A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 11, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Sandeep Kumar GOEL
  • Publication number: 20160019332
    Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.
    Type: Application
    Filed: September 29, 2015
    Publication date: January 21, 2016
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Publication number: 20160011257
    Abstract: A method of detecting one or more faults in a semiconductor device that includes generating one or more secondary node lists from a primary node list. The primary node list includes one or more nodes. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists. The method also includes generating a test pattern set from the secondary node list and a fault list. The fault list identifies one or more faults.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventor: Sandeep Kumar GOEL
  • Patent number: 9222983
    Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sandeep Kumar Goel
  • Publication number: 20150355277
    Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Publication number: 20150347664
    Abstract: A method of detecting one or more faults in a semiconductor device that includes generating a first test pattern set from a primary node list and a fault list. The primary node list includes one or more nodes and the fault list identifies one or more faults. The method also includes generating one or more secondary node lists from the primary node list and generating a second test pattern set from at least the first test pattern set and the secondary node list. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 3, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar GOEL, Yuan-Han LEE
  • Patent number: 9194913
    Abstract: A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sandeep Kumar Goel
  • Patent number: 9158881
    Abstract: Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Publication number: 20150234979
    Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.
    Type: Application
    Filed: May 6, 2015
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ashok MEHTA, Stanley JOHN, Kai-Yuan TING, Sandeep Kumar GOEL, Chao-Yang YEH
  • Patent number: 9110136
    Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Publication number: 20150216030
    Abstract: An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Mark Semmelmeyer, Sandeep Kumar Goel
  • Publication number: 20150198997
    Abstract: Provided is a system that includes a monitoring unit, processing units, and peripheral units. Each of the processing units is linked to the monitoring unit and each of the peripheral units is also linked to the monitoring unit. Each of the processing units is configured to transmit requests to and subsequently receive responses from at least one of the peripheral units through the monitoring unit. The monitoring unit is configured to measure and store delays between the responses and the respective requests.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Ashok Mehta
  • Patent number: 9054101
    Abstract: An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mark Semmelmeyer, Sandeep Kumar Goel
  • Patent number: 9047432
    Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ashok Mehta, Stanley John, Kai-Yuan Ting, Sandeep Kumar Goel, Chao-Yang Yeh