Abstract: The present invention relates to controlled-release pharmaceutical dosage forms comprising a solid dispersion of a poorly water-soluble or insoluble drug with improved solubility and thus improved dissolution in an aqueous medium. The invention further discloses a process of preparation of these controlled-release dosage forms.

Abstract: This invention is related to methods and systems for vector assembly for transgenic plants. A uniform modular process is used to reduce cycle time and the methods and systems provided herein can increase cloning throughput using multiple-well plates, for example 96-well plates. In some embodiments, the methods and systems provided herein eliminate or reduce the need for sequencing confirmation because no PCR is involved in the vector assembly process.

Abstract: An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.

Abstract: Conditions are enforced to prevent unintended deletion of data stored by a data storage system. For example, to delete a collection of data, a condition on the collection of data's size may be enforced. The collection may be required to be empty, for example. In addition, a condition that there not exist a pending data processing operation that can affect fulfillment of the condition on the collection of data's size is also enforced.

Abstract: Aspects of geotagged communications are described herein. In one embodiment, a data unit including a geotag field is received over an ingress port of a network component. In turn, the network component may determine a path for forwarding the data unit to a location associated with the geotag field and with reference to a forwarding decision index. The path may include a least distance hop or a least distance route for forwarding or routing the data unit. With reference to the forwarding path, the network component may identify an egress port for forwarding the data unit. The network component may also forward the data unit over the egress port. According to other aspects, geolocation data may enable a network component to implement geotag-based virtual local area networks, geotag-based multiprotocol label switching, geotag-based fault detection and isolation, or geotag-based firewalls and fencing in wired routers or switches, for example.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract: The present disclosure generally relates to devices and procedures for the development of glucose oxidase-bound electrodes by a covalent binding of glucose oxidase on amine-functionalized electrodes. More particularly, the present disclosure is related to covalently-bound enzyme-coated electrodes that are leach-proof and highly stable for continuous glucose monitoring. The glucose oxidase-bound electrodes are employed for the development of a mediator-less electrochemical glucose sensing procedure having no interference from biological substances and drugs.

Abstract: A device with dynamically tunable heterogeneous latencies includes an input port configured to receive a packet via a network, and a processing module configured to determine multiple values corresponding to a number of qualifying parameters associated with the packet. The processing module may use the values to generate a selector value and may allocate a latency mode to the packet based on the selector value.

Abstract: Methods and apparatus for enhanced radio resource control (RRC) reestablishment in a communication system include addressing repeated radio link failures (RLFs). For example, the methods and apparatus include incrementing a counter value associated with a first cell based on a detection of a RLF by a user equipment (UE) in a RRC connected state with the first cell. The methods and apparatus further include determining that the counter value meets or exceeds a first barring threshold value within a cell barring evaluation time duration. Additionally, the methods and apparatus include prohibiting the UE from performing an RRC reestablishment procedure with the first cell for a first barring time duration.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using Zea mays metallothionein-like gene regulatory elements.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Setaria italica ubiquitin genes.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Panicum virgatum ubiquitin genes.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Brachypodium distachyon ubiquitin genes.

Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using the regulatory elements, including the promoters and/or 3?-UTRs, isolated from Brachypodium distachyon ubiquitin genes.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.