Abstract: A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.

Abstract: A method includes shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together, outputting a second logic sequence from each of the plurality of scan blocks in the first scan chain to a respective scan block in a second scan chain, and shifting a third logic sequence out of the second scan chain. At least one improperly functioning scan block of the first scan chain is identified based on the third logic sequence shifted out of the second scan chain.

Abstract: System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.

Abstract: Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.

Abstract: The integrated circuit (10) has an internal power supply domain with a power supply voltage adaptation circuit (14) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit (16) in the integrating circuit (10). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.

Abstract: A method is disclosed for high-speed processing of structured application messages in a network device. According to one aspect, a network device receives a set of message classification rules that have been prepared beforehand by a system administrator or customer. The system analyzes the message classification rules to determine what part(s) of the message are necessary to classify a message according to the message classification rules. This allows the system to consider only the relevant parts of the message and ignore the rest of the message. The system extracts the portion of the message necessary for classifying the message and classifies the message using the values of the extracted information and the message classification rules. A unique sequence of operations is implied by the message classification and those operations must then be applied to the message.

Abstract: Provided are constructs and methods for expressing multiple genes in plant cells and/or plant tissues. The constructs provided comprise at least one bi-directional promoter link to multiple gene expression cassettes. In some embodiments, the constructs and methods provided employ a bi-directional promoter based on a minimal core promoter element from a Zea mays Ubiquitin-1 gene, or a functional equivalent thereof. In some embodiments, the constructs and methods provided allow expression of genes between three and twenty.

Abstract: The present invention relates to pharmaceutical compositions that include a combination of a biguanide present in an extended-release form and a low dose antidiabetic agent present in an immediate-release form. The present invention further relates to processes for preparing such compositions.

Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.

Abstract: A method and system for calculating pipeline integrity business risk score for a pipeline network is provided. The method includes a step of first calculating a structural risk score, an operational risk score and a commercial risk score for each pipeline segment in a pipeline network. The method further includes calculating pipeline integrity business risk score for each pipeline segment. The structural risk score, operational risk score, commercial risk score and pipeline integrity business risk score for each pipeline segment is rolled-up to calculate the respective risk scores of a pipeline network. The rolled-up risk scores are calculated by computing weight factors for each pipeline segment, relative risk scores weight of each pipeline segment and relative risk scores contribution of each pipeline segment. The system of the invention comprises executable files, dynamic linked libraries and risk score computing modules configured to display the risk scores using a dashboard.

Abstract: A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract: Embodiments of the invention relate to a method for retrieving event data. The method includes receiving, by an event management device, an event query requesting event data corresponding to a filtering parameter, the filtering parameter being a non-indexed database parameter of an Internet Protocol database (IPDB). The method includes generating, by the event manager device, a Bloom filter value based upon the filtering parameter included in the event query. The method includes comparing, by the event manager device, the Bloom filter value with a Bloom filter index entry of an index file of the IPDB, the index file corresponding to the requested event data, the Bloom filter index entry indicating existence of the filtering parameter as part of the IPDB and reading, by the event manager device, the entry from the index file database when the Bloom filter value matches the Bloom filter index entry.

Abstract: A structure comprises a first die, a second die, an interposer, a third die, and a fourth die. The first die and the second die each have a first surface and a second surface. First conductive connectors are coupled to the first surfaces of the first and second dies, and second conductive connectors are coupled to the second surfaces of the first and second dies. The interposer is over the first and second dies. A first surface of the interposer is coupled to the first conductive connectors, and a second surface of the interposer is coupled to third conductive connectors. The third and fourth dies are over the interposer and are coupled to the third conductive connectors. The first die is communicatively coupled to the second die through the interposer, and/or the third die is communicatively coupled to the fourth die through the interposer.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: An apparatus can receive and transfer data and energy between adjacent apparatus in a chain. Each apparatus comprises an input antenna for receiving an input signal which is tuned and impedance matched for a receiver and demodulator in a control circuit. The demodulated signal is provided as input to a transmitter module to create an output signal. The input signal is then impedance transformed to generate a sufficient voltage to energize a power supply which charges a battery. The input signal and the output signal can be a radio signal, a magnetic induction signal, or a combined radio and magnetic induction signal. A controller in the control circuit monitors the condition of the battery and power supply and controls a switch operable to selectively power parts of the apparatus dependently upon their monitored condition.

Abstract: Application message payload data elements are transformed within a network infrastructure element such as a packet data router or switch. The network element has application message transformation logic for receiving one or more packets representing an input application message logically associated with OSI network model Layer 5 or above; extracting an application message payload from the input application message; identifying one or more first content elements in the application message payload; transforming the first content elements into one or more second content elements of an output application message; and forwarding the output application message to a destination that is identified in the input application message. Transformations performed in the network element can include field reordering, field enrichment, field filtering, and presentation transformation.

Abstract: A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.

Abstract: In one aspect, embodiments of a method of configuring rules for SCADA data of a wind farm are described. One embodiment comprises receiving supervisory control and data acquisition (SCADA) data for a wind farm comprised of one or more wind turbines. The SCADA data includes parameters for the wind farm. At least a portion of the SCADA data for a selected group of the wind farm parameters is dynamically configured using a graphical user interface (GUI) that interfaces with a rules engine. The SCADA data is configured using one or more operators. At least a portion of the dynamically configured data is output.