Patents by Inventor Sandeep Kumar

Sandeep Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interposer Defect Coverage Metric and Method to Maximize the Same
    Publication number: 20150058819
    Abstract: Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets.
    Type: Application
    Filed: November 22, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • System and method for testing stacked dies
    Patent number: 8966419
    Abstract: Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • BATTERY MANAGEMENT APPARATUS AND METHOD
    Publication number: 20150048673
    Abstract: A battery management apparatus and method for use in an electrical vehicle has a plurality of individual batteries 34 provided within a battery pack 10. The battery pack is coupled to power vehicle traction 12 and a plurality of individually connectable vehicle appliances 18-26. A monitor keeps track of charge state by means of a battery monitor 44 on each battery relaying instant current to a processor 27. In a first embodiment, a charge allocation profile for the whole battery pack 10 is used where different appliances 18-26 have different amounts of charge capacity allocated to them and are disconnected when discharge exceeds their allocation and are reconnected during charging when their charge is again found. In a second embodiment, individual batteries 34 and appliances 18-26 are connected within a network configuration allowing anything to be connected to anything else.
    Type: Application
    Filed: January 11, 2013
    Publication date: February 19, 2015
    Inventor: Sandeep Kumar Chintala
  • Flame Retardant Composition, Fibers, Process of Preparation and Applications Thereof
    Publication number: 20150050858
    Abstract: The present disclosure provides a flame retardant composition as well as fibers comprising a matrix and an additive wherein each of the matrix and the additive is independently selected from Ultra High Molecular weight Polyethylene (UHMPE) and Polyphosphazene (PPZ) and wherein, when the matrix is UHMPE, the additive is PPZ and when the matrix is PPZ, the additive is UHMPE. Further the present disclosure provides a process of melt spinning the flame retardant composition of a matrix and an additive wherein each of the matrix and the additive is independently selected from UHMPE and PPZ and wherein, when the matrix is UHMPE, the additive is PPZ and when the matrix is PPZ, the additive is UHMPE to obtain flame retardant fibers.
    Type: Application
    Filed: September 20, 2013
    Publication date: February 19, 2015
    Inventors: Arvind Kumar Saxena, Vineeta Nigam, Sandeep Kumar, Anjlina Kerketta
  • DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips
    Patent number: 8914692
    Abstract: A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sandeep Kumar Goel
  • PROBE CARD PARTITION SCHEME
    Publication number: 20140354322
    Abstract: A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 4, 2014
    Inventors: Sandeep Kumar GOEL, Mill-Jer WANG
  • Crystalline forms of cabazitaxel and process for preparation thereof
    Patent number: 8901322
    Abstract: The present invention provides Crystalline Forms of 4-acetoxy-2?-benzoyloxy-5?-20-epoxy-1-hydroxy-7?,10?-dimethoxy-9-oxotax-11-en-13?-yl(2R,3S)-3-tert-butoxycarbonylamino-2-hydroxy-3-phenylpropionate, i.e Cabazitaxel. The present invention also discloses methods for the preparation of Crystalline Forms of Cabazitaxel and pharmaceutical compositions thereof.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 2, 2014
    Assignee: Fresenius Kabi Oncology Limited
    Inventors: Saswata Lahiri, Rajesh Srivastava, Bhuwan Bhaskar Mishra, Shatrughan Sharma, Vijay Ojha, Nilendu Panda, Sandeep Kumar, Sonu Prasad
  • SCALABLE FORWARDING TABLE WITH OVERFLOW ADDRESS LEARNING
    Publication number: 20140348170
    Abstract: A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Yafan AN, Sandeep KUMAR, Gunes AYBAY, Rakesh DUBEY
  • GREEN PROCESS TO HYDROLYZE CARBOHYDRATES FROM TOBACCO BIOMASS USING SUBCRITICAL WATER
    Publication number: 20140331993
    Abstract: Processes for recovering sugars and nicotine from a tobacco biomass include feeding a biomass of tobacco plants and subcritical water to a reactor, hydrolyzing the biomass of tobacco plants with the subcritical water at a temperature between about 150° C. and 305° C. and recovering a liquid product and a solid product from the reactor, wherein the liquid product contains water-soluble sugars and nicotine.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicants: OLD DOMINION UNIVERSITY RESEARCH FOUNDATION, TYTON BIOSCIENCES
    Inventors: Sandeep KUMAR, Jose Luis Garcia MOSCOSO, Iulian BOBE, Peter MAJERANOWSKI
  • DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips
    Patent number: 8873320
    Abstract: A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Tze-Chiang Huang
  • VLAN Bridging Path for Virtual Machines in MVRP Environment without Administrator Intervention
    Publication number: 20140294012
    Abstract: A bi-directional VLAN bridging path is created on an edge switch in an MVRP environment without administrator intervention using a virtual network profile (VNP) feature running on the edge switch. The VNP feature is configured to detect a device coupled to a port of the edge switch, learn the Medium Access Control (MAC) address of the device on a MVRP-VLAN and automatically convert the MVRP-VLAN to a VNP-Dynamic-VLAN corresponding to a static VLAN to create a bi-directional VLAN Port Association (VPA) for the device.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicants: ALCATEL-LUCENT INDIA LIMITED, ALCATEL-LUCENT USA INC.
    Inventors: Anil Nagarajan, Sandeep Kumar, Arvind Kubendran, Jagjeet S. Bhatia, Edgard Vargas
  • Method And Apparatus For Peer Node Synchronization
    Publication number: 20140293827
    Abstract: A method and apparatus for facilitating synchronization of network nodes in an MC-LAG (multi-chassis link aggregation) configuration. Each of two nodes communicate with each other in such a manner as to enable data traffic to be handled efficiently by either.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Inventors: Sandeep Kumar, Anil Nagarajan, Arvind Kubendran, Jagjeet Bhatia, Edgard Vargas, Lathakannan Arumugam, Ashokkumar Rajendran
  • METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR DETERMINING A TIME-TO FAILURE OF AN ASSET
    Publication number: 20140288908
    Abstract: The present invention provides a method and system for determining a time-to-failure of an asset. A probabilistic non-linear model of a limit state of the asset is simulated and approximated by a predetermined set of particles. A numerical scheme for computation of a conditional probability distribution of a size of the defect, based on a value of the limit state is evaluated. A set of future values of a weight factor of each particle is predicted based on an initial assigned value. The predicted set of future values can be updated on capturing a new set of inspection data. A probability of the time-failure of the asset is estimated by summing the weight factor of a set of particles, the set of particles comprising particles at which the limit state is less than a zero limit threshold.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 25, 2014
    Applicant: Infosys Limited
    Inventors: HARI MANASSERY KODUVELY, GOPICHAND AGNIHOTRAM, SANDEEP KUMAR DEWANGAN, PREETI PISUPATI
  • METHOD AND APPARATUS FOR INTERCONNECT TEST
    Publication number: 20140281773
    Abstract: A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Saman M.I. Adham
  • SYSTEM AND METHOD TO CLEAR AND REBUILD DEPENDENCIES
    Publication number: 20140281404
    Abstract: A data processing system and method of clearing and rebuilding dependencies, the data processing method including changing a counter associated with a first entry in response to selecting a second entry; comparing the counter with a threshold; and indicating that the first entry is ready to be selected in response to comparing the counter with the threshold; wherein the first entry is dependent on the second entry.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Ravi Iyengar, Sandeep Kumar Dubey
  • EFFICIENT WAY TO CANCEL SPECULATIVE 'SOURCE READY' IN SCHEDULER FOR DIRECT AND NESTED DEPENDENT INSTRUCTIONS
    Publication number: 20140281431
    Abstract: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Ravi IYENGAR, Bradley Gene BURGESS, Sandeep Kumar DUBEY
  • Probe card partition scheme
    Patent number: 8836363
    Abstract: A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Mill-Jer Wang
  • Reducing design verification time while maximizing system functional coverage
    Patent number: 8826202
    Abstract: A system for functional verification of a chip design includes the chip design, a test generator, a test bench, a verification tool, and a coverage tool. The coverage tool is configured to receive chip design, user input, and coverage files from the verification tool to generate information for the test generator to improve the test coverage of the verification tool. The method includes receiving a chip design, functionally testing the chip design, generating coverage files, receiving user options, including a coverage basis, a report basis, and a defined coverage, calculating coverage impact and new overall coverage using the defined coverage and coverage files, and ranking each report basis according to coverage impact of each coverage basis.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • SUBSTITUTED 4-ARYLTHIAZOLES AND PROCESS OF PREPARATION THEREOF
    Publication number: 20140235863
    Abstract: The present invention relates to novel substituted 4-arylthiazoles, their preparation, and to their use as therapeutic agents, particularly in the prevention or treatment of tuberculosis.
    Type: Application
    Filed: March 1, 2012
    Publication date: August 21, 2014
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Supriya Singh, Kuldeep Kumar Roy, Sandeep Kumar Sharma, Ranjana Srivastava, Vinita Chaturvedi, Anil Kumar Saxena
  • Scalable forwarding table with overflow address learning
    Patent number: 8804735
    Abstract: A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: August 12, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Yafan An, Sandeep Kumar, Gunes Aybay, Rakesh Dubey