Patents by Inventor Sandeep Kumar

Sandeep Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230306415
    Abstract: Rules and triggers for initiating and generating transactions can be dynamically and automatically created by a computing device based on learning behaviors for a knowledgebase. Additionally, payment devices may be intelligently selected for transactions using various contextual attributes. Transaction generation and payment device selection may occur within a particular network such as an Internet of Things (IoT) network where devices are interconnected and capable of processing data and instructions. Such a network may be associated with a user or location or organization, and may conform to a specific communication protocol. Payment device selection may consider a variety of factors including communication security, encryption, location, and benefits.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Puneetha Polasa, Bhagya Lakshmi Sudha Lavanya Mallidi, Udaya Kumar Raju Ratnakaram, Sandeep Kumar Chauhan, Jagadish Reddy
  • Publication number: 20230306404
    Abstract: A method and apparatus for dynamically selecting a transaction processing device in a multi-device network is provided. A transaction processing device may be used to generate, approve, execute, and otherwise process transactions for devices in the multi-device network. A device selection platform may determine which of a plurality of devices is to serve as the transaction processing device based on a variety of factors such as battery life, processing power, communication connectivity, storage capacity and the like. The devices may be prioritized and ranked based on these factors. The platform may further monitor for changes in the network and dynamically update the prioritization and ranking and/or selection of the transaction processing device.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Puneetha Polasa, Bhagya Lakshmi Sudha Lavanya Mallidi, Udaya Kumar Raju Ratnakaram, Sandeep Kumar Chauhan
  • Publication number: 20230306428
    Abstract: Arrangements for smart tracking and dynamic authentication are provided. In some aspects, a user may be detected and image data of the user may be captured. The image data may be analyzed using one or more facial recognition techniques to determine whether the user is a recognized user. A connection may be established between an entity system and a user computing device and a type of connection may be transmitted to a computing platform for analysis. The computing platform may identify one or more authentication requirements based on the type of connection. The authentication requirements may be transmitted to one or more devices and executed. Authentication response data may be received and compared to prestored authentication data and, if the user is authenticated, an instruction or command causing a connection to be established between the user computing device and an entity computing device may be generated and transmitted.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Udaya Kumar Raju Ratnakaram, Bhagya Lakshmi Sudha Lavanya Mallidi, Puneetha Polasa, Sandeep Kumar Chauhan
  • Patent number: 11760983
    Abstract: This disclosure provides various TcBuster transposases and transposons, systems, and methods of use.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 19, 2023
    Assignee: B-Mogen Biotechnologies, Inc.
    Inventors: David Largaespada, Branden Moriarity, Beau Webber, Neil Otto, Sandeep Kumar, Leah Hogdal
  • Publication number: 20230289099
    Abstract: An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: Intel Corporation
    Inventors: Yasir Mohsin Husain, Xuming Zhao, Kevin E. Arendt, Sandeep Kumar Guliani
  • Patent number: 11757649
    Abstract: Systems, computer program products, and methods are described herein for enhanced authentication framework using multi-dimensional hashing. The present invention is configured to electronically receive, from a computing device of a user, a resource transfer request; retrieve, from an authentication database, a multi-dimensional hash for a first set of data files for the user and a user identification artifact; retrieve, from the computing device of the user, a second set of data files matching the user identification artifact; initiate an asynchronous hash processing engine on the second set of data files; generate, using the asynchronous hash processing engine, a multi-dimensional hash for the second set of data files; compare the multi-dimensional hash for the first set of data files with the multi-dimensional hash for the second set of data files to determine a match; and authorize the resource transfer request based on at least determining the match.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 12, 2023
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Udaya Kumar Raju Ratnakaram, Sandeep Kumar Chauhan, Sriram Balasubramanian
  • Patent number: 11748755
    Abstract: Apparatus and methods for securing a transaction. The apparatus may include a transaction instrument. The transaction instrument may be configured to exchange transaction data to effect a transaction by engagement of a microprocessor with a transacting party. The transaction instrument may include a sensor. The sensor may be configured to sense an environmental parameter. The sensor may be in electrical communication with the microprocessor. The apparatus may run analysis using a distributed model. In the distributed model, heavy processing may be performed at the pattern registration platform, and light processing may be performed on on-board processors on the transaction instrument. The environmental parameter may be associated with one or more behaviors of the user.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: September 5, 2023
    Assignee: Bank of America Corporation
    Inventors: Sandeep Kumar Chauhan, Jagadish Reddy
  • Patent number: 11750666
    Abstract: Systems, methods and apparatus are provided for a Dynamic Group Session Data Access Protocol. The system may monitor participant input in a group interactive session. The system may be trained to monitor and understand the group environment and predict intent of the participant discussion and may predict relevant data. The system may be used by a single participant or by multiple participants. The system may determine the access level of the participants. The system may determine the access level of the data. The system may compare the access level of the participants with the access level of the data. The system may dynamically mask the data if the access level of the participants does not match the access level of the data. The system may create customized views of the data for each participant based on the participant's access level and the access level of the data.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 5, 2023
    Assignee: Bank of America Corporation
    Inventors: Sandeep Kumar Chauhan, Moses Salagala, Swadeep Mekala, Amit Kumar Bidhanya, Shailendra Singh
  • Publication number: 20230272430
    Abstract: Methods and compositions for modulating a target genome are disclosed.
    Type: Application
    Filed: September 1, 2022
    Publication date: August 31, 2023
    Inventors: Anne Helen BOTHMER, Cecilia Giovanna Silvia COTTA-RAMUSINO, William Edward SALOMON, Jacob Rosenblum RUBENS, Robert James CITORIK, Zi Jun WANG, Kyusik KIM, Randi Michelle KOTLAR, Ananya RAY, Robert Charles ALTSHULER, Sandeep KUMAR, Nathaniel ROQUET, Barrett Ethan STEINBERG
  • Publication number: 20230272355
    Abstract: This disclosure provides various SPIN transposases and transposons, systems, and methods of use.
    Type: Application
    Filed: June 4, 2021
    Publication date: August 31, 2023
    Inventors: David Largaespada, Branden Moriarity, Beau Webber, Neil Otto, Sandeep Kumar, Bryan Jones
  • Patent number: 11740976
    Abstract: Techniques for generating a crash-consistent clone of file(s) stored by a distributed file system are described herein. To generate the crash-consistent clone, a coordinator node may identify multiple nodes (e.g., at least a first node and a second node) of the distributed file system that are storing different portions of data of the file. The coordinator node may then send a first command to the multiple nodes to cause each of the multiple nodes to quiesce the file and clone the different portions of the data to generate the crash-consistent clone of the file. The coordinator node may then receive, from the multiple nodes, a status associated with generating the crash-consistent clone of the file. Based at least in part on the status, the coordinator node may send a second command to the multiple nodes to cause each of the multiple nodes to unquiesce the file.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 29, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Chetan Chandrakant Paithane, Sandip Agarwala, Sandeep Kumar, Chandramouli Subramanian
  • Publication number: 20230269294
    Abstract: Domain-based server-selection computer-implemented processes and machines implement an extension of RAFT consensus for leader selection based on patterns of update data proximity. Accounts involved in payment or other transactions are maintained as “sharded” data across data store instances that are split into shards according to their temporal activity. If the domain attributes for a node exceed a threshold and are greater than the other nodes, the node is designated as a leader node and the others are designated as follower nodes. This provides an additional optimization in network performance by introducing insights in normal operations within a domain in a distributed network. If the domain attributes do not exceed the threshold and/or are not greater than the other nodes, a traditional consensus algorithm is used to select leader and follower nodes.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 24, 2023
    Inventors: Yash Sharma, Sandeep Kumar Chauhan
  • Patent number: 11734658
    Abstract: A method for facilitating transactions by tenants in a multi-tenant architecture system is discussed. The method includes generating, with a multi-tenant computer system, a first representation of an entity in a first hierarchical data structure associated with an entity interface tenant of the multi-tenant computer system. The method includes receiving, with the multi-tenant computer system, a set of entity-specific policies useable to generate requests to individual ones of a plurality of transaction processing computer systems. The method includes generating, with the multi-tenant computer system, a second representation of the entity in a second hierarchical data structure associated with a particular transaction processing service tenant of a plurality of transaction processing service tenants of the multi-tenant computer system.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 22, 2023
    Assignee: PayPal, Inc.
    Inventors: Prashant Jamkhedkar, Savio A. Menezes, Sandeep Kumar, Jacqueline Koesters, Benjamin Matthew Ronick, Daniel O'Connor, Tiffany Wood, Aravindan Ranganathan, Norihiro Edwin Aoki, Jeffrey David Meyer, Justin Matthew White
  • Publication number: 20230261659
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230260907
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230259148
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230261001
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i?1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M?1, wherein a sum of all Xj voltages for j=1:(M?1) is greater than 0.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230262133
    Abstract: A system includes a memory and a processor. The processor is configured to determine that a user has ceased using a first device while the user was in an active user session with an application. The processor is further configured to determine a last user interface with which the user interacted on the first device and to determine user-supplied information from the last user interface. The processor is further configured to determine that the user is attempting to start a new user session with the application on a second device, and in response, display a message on the second device inquiring if the user wishes to continue with the last user interface. The processor is further configured to display a new user interface on the second device that corresponds to the last user interface and display the user-supplied information from the last user interface in the new user interface.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Sandeep Kumar Chauhan, Sneha Padiyar, Eshita Gupta
  • Publication number: 20230261656
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input directly connected to an output of at least one digital logic cell of the second plurality, or (b) an output directly connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Patent number: 11727177
    Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: August 15, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee