Abstract: A method for making a cell capacitor of a semiconductor device such as a dynamic random access memory includes steps for increasing the height of a capacitor electrode. With increased height, the capacitance of the fabricated capacitor is increased while allowing high integration.

Abstract: A separable circuit breaker includes a separate trip apparatus portion, having a trip apparatus and a trip apparatus container, and a switching apparatus portion having a switching apparatus and a switching apparatus container. The switching apparatus and trip apparatus are connectable by connection terminals in a lower part of the respective containers. The trip apparatus portion also includes a trip apparatus cover connected to an upper portion of the trip portion container and an assistant cover rotatably connected to an upper portion of the trip apparatus cover. The assistant cover allows access to the trip apparatus. The trip appartus includes a bimetal element and an armature. The switching apparatus portion includes a crossbar and a handle. The crossbar is connected and engaged with the armature according to deformation of the bimetal element such that current flow through the circuit breaker can be opened by rotation of the crossbar when an overcurrent exists.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having an active region and an inactive region, a gate electrode formed on the semiconductor substrate over the active region, wherein a gap exists between the semiconductor substrate and the gate electrode, and source and drain regions formed beneath a surface of the semiconductor substrate at both sides of the gate electrode.

Abstract: A method for fabricating an isolation layer in a semiconductor device, includes the steps of forming a pad oxide layer on a substrate and sequentially forming a first thin nitride layer, a polysilicon layer and a second nitride layer on the pad oxide layer; selectively and sequentially dry-etching the second nitride layer, polysilicon layer, first nitride layer and pad oxide layer to expose a portion of the substrate corresponding to a field region and to form an active region pattern; growing an oxide layer on the exposed portion of the substrate in the field region; carrying out nitridation onto the polysilicon layer to form a nitride layer on the side of the active region pattern; and performing field oxidation to form a field oxide layer in the field region.

Abstract: A method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability is disclosed. The method includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions of the first conductivity-type into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate.

Abstract: An MOSFET (metal oxide semiconductor field effect transistor) and a method for fabricating the same in which charge trap is prevented at sidewall spacer of a gate insulating film are disclosed, the MOSFET including a gate insulating film and a gate electrode successively formed on a semiconductor substrate of first conductivity type; an insulating sidewall spacer formed on sides of the gate electrode; a vacuum region formed between the semiconductor substrate and the insulating sidewall spacer; and source/drain regions formed beneath surface of the semiconductor substrate at side of the gate electrode.

Abstract: A method for fabricating an isolation layer of a semiconductor device defines an active region and an isolation region on a semiconductor substrate. An active pattern is formed on the active region of the semiconductor substrate and the active pattern includes a first insulating layer and a first oxidation stop layer formed on the first insulating layer. A first isolation layer is grown over the substrate corresponding to the isolation region and the first isolation layer is selectively etched by using the first oxidation stop layer as a mask. A sidewall spacer is formed adjacent to the active pattern including a remaining portion of the first isolation layer, and the sidewall spacer includes a second insulating layer and a second oxidation stop layer formed on the second insulating layer. A second isolation layer is grown over the substrate.

Abstract: A fabrication method for a capacitor of a stack-type DRAM cell includes forming a first insulating film, an anti-etching film, and a first conductive film on a substrate by which a switching transistor and a bit line previously are buried, forming a patterned second insulating film on the first conductive film, forming a second conductive film on the first conductive film having the patterned second insulating film thereon, dry-etching the first and second conductive film to expose a portion of the surface of the anti-etching film therethrough, forming a contact hole by etching the exposed surface of the anti-etching film and the first insulating film therebeneath, forming a third conductive film over the surfaces of the first and the second conductive films, including the contact hole therebetween, forming a planarized fourth insulating film over the third conductive film, etching the fourth insulating film to expose a portion of the surface of the anti-etching film above the bit line and then etching the th