Abstract: A transistor and a method for manufacturing the same are disclosed. One cell transistor having silicon-insulator-silicon (“SIS”) structure and two cell transistors having silicon-oxide-nitride-oxide-silicon (“SONOS”) structure constitute the transistor of the present invention which can store 2 bits. The cell transistor having SIS structure and the cell transistors having SONOS structure share one common gate electrode so that the transistor of the present invention requires only one voltage generation and control circuit.

Abstract: An image forming apparatus having an image forming part to apply developer to a recording medium to form an image, the image forming apparatus including a developer transporting pipe through which developer is transported to the image forming part, a first storing part to store a first amount of the developer and to supply the developer to an upstream part of the developer transporting pipe, at least a second storing part to store at least a second amount of the developer and to supply the developer to a downstream part of the developer transporting pipe, and a transporting device, disposed along the developer transporting pipe, to transport the developer supplied by the first storing part and the second storing part to the image forming part with the upstream part of the developer transporting pipe having a different transport flow rate than the downstream part of the developer transporting pipe.

Abstract: Disclosed herein is a method for fabricating a memory device. According to the present invention, a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, and a semiconductor substrate in the recess gate region is etched. Accordingly, a silicon horn in the recess gate region is prevented from being formed, thereby increasing a margin of the etching process.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor substrate, a gate oxide film that is formed on the semiconductor substrate below the floating gate with respect to the tunnel oxide film, wherein the gate oxide film is formed along the boundary of some of the bottom and side of the floating gate, and floating nitride films that are buried at gaps between the gate oxide film formed on the semiconductor substrate and the gate oxide film formed along the boundary of some of the bottom and side of the floating gate, wherein the floating nitride films serve as a trap center of a hot charge and store 1 bit charge. The transistor of the semiconductor device can operate as a 2-bit or 3-bit cell transistor.

Abstract: The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate.

Abstract: The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface of a channel region. This structure allows the formation of a relatively a thick channel region and decreases the sensitivity of characteristics of the device dependent upon the thickness of the channel region.

Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insualting film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.

Abstract: An image forming apparatus is provided that forms an image with liquid developer, and a method thereof. The image forming apparatus includes a plurality of photoconductors on which developer images having carrier rates different from each other are formed with corresponding liquid developers. An image transfer member is disposed to form transfer nips with the respective photoconductors in such a manner that the developer images of the respective photoconductors are overlappingly transferred onto the image transfer member according to a transfer order predetermined on the basis of the carrier rates thereof. The developer images from the respective photoconductors are moved to an image receiving medium.

Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Abstract: An image transfer member, an image transfer device and an image forming system employing the image transfer member and device are disclosed. The image transfer member comprises a base layer, and a surface layer formed from a semi-conductive material above the base layer to receive the developer image transferred from the photoconductor. The surface layer forms a contact inscribed angle ? in the range of 10° to 50° between the surface thereof and the developer image. The image transfer member has a voltage-current characteristic exhibiting a current density (CD) in the range of 0.6 ?A/cm2?CD?1.5 ?A/cm2 at 1 KV voltage, and a voltage decay characteristic exhibiting a voltage decay time (DT) in the range of 0.4 sec?DT?3 sec for the voltage decay from 500 V to 100 V. The present invention avoids a transfer defect such as transfer void produced by breakdown caused when a high bias voltage is applied to a developer image having a high electric charge and to significantly improve the transfer efficiency.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: Transistor of semiconductor device and method for manufacturing the same are disclosed. The transistor comprises a channel region formed on a sidewall of a silicon fin extruding above a device isolation region. The silicon fin serves as an active region and is shorter in length so as to be spaced apart from an adjacent gate electrode. The width of the channel region is determined by the height of the silicon fin. The source/drain region of the transistor is disposed at an upper surface and the sidewall of the silicon fin to increase the contact region.

Abstract: An apparatus for uniformly supplying the liquid developer and an image forming apparatus having the same are provided. The developer supplying apparatus includes a manifold connected to a connection tube for supplying a liquid developer from an outside and having a developer inlet through which the liquid developer flows into a developing chamber, and a developer dispersion unit, disposed in the developing chamber and located adjacent to an upper part of the developer inlet, for guiding the liquid developer flowing into the developing chamber through the developer inlet so that the liquid developer is dispersed in a horizontal direction. The liquid developer flowing into the lower part of the developing chamber does not directly move toward the upper part of the developing chamber, but is dispersed in a horizontal direction, so that the liquid developer is uniformly dispersed into the whole part of the developing chamber.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: Disclosed herein is a method for producing a multi-wavelength semiconductor laser device. The method comprises the steps of: forming first and second nitride epitaxial layers in parallel on a substrate for growth of a nitride single crystal; separating the first and second nitride epitaxial layers from the substrate; attaching the separated first and second nitride epitaxial layers to a first conductivity-type substrate; selectively removing the first and second nitride semiconductor epitaxial layers to expose a portion of the first conductivity-type substrate and to form first and second semiconductor laser structures, respectively; and forming a third semiconductor laser structure on the exposed portion of the first conductivity-type substrate.

Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Abstract: A power control unit of a fuel cell hybrid vehicle includes a first switching unit, a second switching unit, and a control unit. One terminal of the first switching unit is connected to a fuel cell stack and to an anode of a DC/DC converter in parallel, and the other terminal is connected to an inverter. One terminal of the second switching unit is connected to the inverter and to a cathode of the DC/DC converter in parallel, and the other terminal is connected to a cathode of the fuel cell stack. The control unit switches contact points of the first and the second switching units to selectively supply a voltage from one of the fuel cell stack and a battery to a motor.