Abstract: The present invention discloses method for manufacturing semiconductor device employing an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film is formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film using the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: The present invention discloses a method for manufacturing semiconductor device wherein a channel implant process of a transistor in a DRAM is performed in a self-aligned manner without using any mask. In accordance with the method, a device isolation film defining an active region on a semiconductor substrate. The device isolation film extrudes upward higher than the active region. The active region is subjected to a tilt ion implant process for implanting a impurity into the active region from two directions using the device isolation film as a mask so that a impurity concentration of the active region adjacent to the device isolation film is one half of that of the active region between the active region adjacent to the device isolation film. A stacked structure of a gate oxide film and a gate electrode are formed on the active region to complete the formation process of the semiconductor device.

Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.

Abstract: The present invention discloses method for manufacturing semiconductor device employing an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film is formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film using the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.

Abstract: The present invention discloses a method for manufacturing semiconductor device wherein a channel implant process of a transistor in a DRAM is performed in a self-aligned manner without using any mask. In accordance with the method, a device isolation film defining an active region on a semiconductor substrate. The device isolation film extrudes upward higher than the active region. The active region is subjected to a tilt ion implant process for implanting a impurity into the active region from two directions using the device isolation film as a mask so that a impurity concentration of the active region adjacent to the device isolation film is one half of that of the active region between the active region adjacent to the device isolation film. A stacked structure of a gate oxide film and a gate electrode are formed on the active region to complete the formation process of the semiconductor device.

Abstract: The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is formed in a cell region of a semiconductor substrate before a source/drain region is formed in a peripheral circuit region of the semiconductor substrate using an epitaxially grown silicon film in a high temperature process, to obtain a contact plug having a high filling characteristic and a low contact resistance. In addition, additional ion-implantation process of a P type impurity in the subsequent bit line contact formation can be omitted to simplify the fabrication process. The method is suitable for the high speed merged DRAM logic process to achieve the high speed operation of the semiconductor device, and improves a process yield and reliability of the semiconductor device.

Abstract: A power control unit of a fuel cell hybrid vehicle includes a first switching unit, a second switching unit, and a control unit. One terminal of the first switching unit is connected to a fuel cell stack and to an anode of a DC/DC converter in parallel, and the other terminal is connected to an inverter. One terminal of the second switching unit is connected to the inverter and to a cathode of the DC/DC converter in parallel, and the other terminal is connected to a cathode of the fuel cell stack. The control unit switches contact points of the first and the second switching units to selectively supply a voltage from one of the fuel cell stack and a battery to a motor.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is formed in a cell region of a semiconductor substrate before a source/drain region is formed in a peripheral circuit region of the semiconductor substrate using an epitaxially grown silicon film in a high temperature process, to obtain a contact plug having a high filling characteristic and a low contact resistance. In addition, additional ion-implantation process of a P type impurity in the subsequent bit line contact formation can be omitted to simplify the fabrication process. The method is suitable for the high speed merged DRAM logic process to achieve the high speed operation of the semiconductor device, and improves a process yield and reliability of the semiconductor device.

Abstract: A capacitor having a storage electrode and a plate electrode, wherein both are made of metal or metal oxide, a high dielectric film formed between the electrodes, and a method of manufacturing the same. A diffusion prevention film is found at the side of the storage electrode and on the plate electrode. Therefore, the invention prevents deterioration of the property in the dielectric film due to penetration of hydrogen ions during a subsequent thermal process thereby improving the reliability of a device.

Abstract: A method for fabricating a MOSFET includes a step of forming an isolation layer on an isolation region of a substrate, to thereby define an active region ion implanting As and P into the active region, and a step of forming a gate on the active region. An ion implanting step of low-concentration impurity using the gate as a mask is performed to form a low-concentration ion-implanted region in a predetermined portion of the substrate which is placed on the right and left sides of the gate. A sidewall spacer on the sides of the gate is formed, and thereafter, and ion implanting high-concentration impurity into the substrate is performed.

Abstract: A test socket connecting an integrated circuit chip to a printed circuit board is disclosed. The test socket includes a horizontal upper portion connected to the integrated circuit chip, a horizontal lower portion connected to the printed circuit board, and an intermediate portion connected between the horizontal upper portion and the horizontal lower portion.

Abstract: A capacitor having a storage electrode and a plate electrode, wherein both are made of metal or metal oxide, a high dielectric film formed between the electrodes, and a method of manufacturing the same. A diffusion prevention film is found at the side of the storage electrode and on the plate electrode. Therefore, the invention prevents deterioration of the property in the dielectric film due to penetration of hydrogen ions during a subsequent thermal process thereby improving the reliability of a device.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same which improve short channel effect and increase current driving force. The semiconductor device includes a first conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate, a sidewall insulating film formed at both sides of the gate electrode, a second conductivity type first lightly doped impurity region and a second conductivity type second heavily doped impurity region formed in the semiconductor substrate at both sides of the gate electrode, a first conductivity type first impurity region for surrounding the second conductivity type first impurity region, and a first conductivity type second impurity region for surrounding the second conductivity type second impurity region.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same which improve short channel effect and increase current driving force. The semiconductor device includes a first conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate, a sidewall insulating film formed at both sides of the gate electrode, a second conductivity type first lightly doped impurity region and a second conductivity type second heavily doped impurity region formed in the semiconductor substrate at both sides of the gate electrode, a first conductivity type first impurity region for surrounding the second conductivity type first impurity region, and a first conductivity type second impurity region for surrounding the second conductivity type second impurity region.

Abstract: An improved method for forming a triple well of a semiconductor device which is capable of more simply and easily forming a triple well without removing an anti-oxidation film.