Abstract: A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si1-xGex) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).

Abstract: The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region.

Abstract: An image forming apparatus is provided that forms an image with liquid developer, and a method thereof. The image forming apparatus includes a plurality of photoconductors on which developer images having carrier rates different from each other are formed with corresponding liquid developers. An image transfer member is disposed to form transfer nips with the respective photoconductors in such a manner that the developer images of the respective photoconductors are overlappingly transferred onto the image transfer member according to a transfer order predetermined on the basis of the carrier rates thereof. The developer images from the respective photoconductors are moved to an image receiving medium.

Abstract: The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to a desired value as well as increasing the operation speed of the transistor and suppress the short channel effect.

Abstract: An image developing unit and an image forming apparatus having the same. The image forming apparatus includes a body, an image developing unit including a frame having a developer supply part into which a developer is introduced, a developing roller rotatably installed on a developing roller support part provided in the frame, and a developer supply auger mounted in the developer supply part so as to provide the developing roller with the developer and formed with a reduction part having a reduced circumferential width, and an image transferring unit to transfer a visible image formed in the image developing unit onto a printing medium, wherein the developer supply auger is installed on the frame such that the reduction part is positioned corresponding to the developing roller support part. An interval between central axes of the developing roller and the developer supply auger becomes narrow, so that a developer is stably supplied to the developing roller.

Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.

Abstract: Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched, thus preventing a silicon horn in the recess gate region from being formed. Accordingly, a margin for the etching process is increased.

Abstract: A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film are formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film uses the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.

Abstract: An image transfer member, an image transfer device and an image forming system employing the image transfer member and device are disclosed. The image transfer member comprises a base layer, and a surface layer formed from a semi-conductive material above the base layer to receive the developer image transferred from the photoconductor. The surface layer forms a contact inscribed angle ? in the range of 10° to 50° between the surface thereof and the developer image. The image transfer member has a voltage-current characteristic exhibiting a current density (CD) in the range of 0.6 ?A/cm2?CD?1.5 ?A/cm2 at 1 KV voltage, and a voltage decay characteristic exhibiting a voltage decay time (DT) in the range of 0.4 sec?DT?3 sec for the voltage decay from 500 V to 100 V. The present invention avoids a transfer defect such as transfer void produced by breakdown caused when a high bias voltage is applied to a developer image having a high electric charge and to significantly improve the transfer efficiency.

Abstract: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree.

Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.

Abstract: A developer agitator of an image forming device capable of improving the electrification rate of a developer is disclosed. The developer agitator includes a rotatable shaft and an agitating wing disposed on the circumferential surface of the shaft. The agitating wing has an uneven part formed to increase the contact area with a developer. The developer agitator can obtain an electrification rate of the developer required for high speed printing, thereby allowing the image forming device to be operated at a high speed.

Abstract: The semiconductor device includes a device isolation structure, a surrounded channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The surrounded channel structure connecting source/drain regions is separated from the semiconductor substrate under the active region by a given distance. The gate electrode surrounds the surrounded channel structure.

Abstract: A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.

Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.

Abstract: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a gate region; a gate insulating film formed over the semiconductor substrate including the protruded fin channel region; and a gate electrode formed over the gate insulating film to fill up the protruded fin channel region.

Abstract: A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess gate region to facilitate a subsequent process for etching a gate electrode without a step difference between the device separating film.

Abstract: The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.