Abstract: The present invention provides templating methods for replicating patterned metal films from a template substrate such as for use in plasmonic devices and metamaterials. Advantageously, the template substrate is reusable and can provide plural copies of the structure of the template substrate. Because high-quality substrates that are inherently smooth and flat are available, patterned metal films in accordance with the present invention can advantageously provide surfaces that replicate the surface characteristics of the template substrate both in the patterned regions and in the unpatterned regions.

Abstract: Disclosed are a light-emitting diode having improved light extraction efficiency and a method for manufacturing same. This light-emitting diode includes: a gallium nitride substrate having an upper surface and a lower surface; and a gallium nitride semiconductor multilayer structure disposed on the lower surface of the substrate, and having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. Herein, the gallium nitride substrate has a main pattern having a protruding portion and a concave portion on the upper surface, and a rough surface formed on the protruding portion of the main pattern. The light-emitting diode is capable of improving light extraction efficiency through the upper surface thereof since the rough surface is formed along with the main pattern on the upper surface of the gallium nitride substrate.

Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.

Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: Exemplary embodiments of the present invention relate to light emitting diodes. A light emitting diode according to an exemplary embodiment of the present invention includes a substrate having a first side edge and a second side edge, and a light emitting structure arranged on the substrate. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A transparent electrode layer including a concave portion and a convex portion is arranged on the second conductivity-type semiconductor layer. A first electrode pad contacts an upper surface of the first conductivity-type semiconductor layer and is located near a center of the first side edge. Two second electrode pads are located near opposite distal ends of the second side edge to supply electric current to the second conductivity-type semiconductor layer.

Abstract: A light-emitting diode includes a substrate, and a light-emitting structure disposed on the substrate. The light-emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A transparent electrode layer including concave portions and convex portions is disposed on the second conductivity-type semiconductor layer. Micro-lenses are disposed on the transparent electrode layer and completely cover the concave portions, and only partially cover the convex portions that are disposed between the micro-lenses.

Abstract: A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.

Abstract: Plasmonic nanocavity arrays and methods for enhanced efficiency in organic photovoltaic cells are described. Plasmonic nanocavities offer a promising and highly tunable alternative to conventional transparent conductors for photovoltaic applications using both organic and inorganic materials systems.

Abstract: A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures.

Abstract: Provided are a light emitting diode (LED) and a method of fabricating the same. The LED includes a unit chip. The unit chip includes a substrate, and a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer which are sequentially stacked on the substrate. A concavo-convex structure having the shape of irregular vertical lines is disposed in a side surface of the unit chip.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.

Abstract: Disclosed herein is an LED chip including electrode pads. The LED chip includes a semiconductor stack including a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode pad located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer; a first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; a second electrode pad electrically connected to the second conductive type semiconductor layer; and an insulation layer interposed between the first electrode pad and the second conductive type semiconductor layer. The LED chip includes the first electrode pad on the second conductive type semiconductor layer, thereby increasing a light emitting area.

Abstract: A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.

Abstract: A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate contact sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: Disclosed is a light emitting diode (LED) comprising a light emitting stacked structure and an electrode structure formed to have a pattern on the light emitting stacked structure. The electrode structure of the LED includes a cluster of reflectors disposed along the pattern on the light emitting stacked structure, and a pad material layer formed to entirely cover the reflectors.

Abstract: A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.