Abstract: A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high.

Abstract: A semiconductor memory device and a method of generating a chip selection signal that enable the analysis of the causes of defects of defective memory devices selected by a user from a system with a plurality of memory devices and the fixing the defects are provided. The semiconductor memory device includes a programming register, an input buffer control circuit, and a chip selection circuit. The programming register activates an output signal in response to an address and a command input from the outside. The input buffer control circuit activates the plurality of data input buffer circuits in response to the output signal of the programming register. The chip selection circuit activates a defect detecting & repairing circuit, such as a repair circuit or a test time shortening circuit, when at least one of output signals of the plurality of data input buffer circuits is in a first logic state.

Abstract: A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.

Abstract: An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut.

Abstract: State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

Abstract: A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.

Abstract: A control signal generating circuit comprising a make-link type fuse is provided. The circuit comprises a first transistor for receiving an input signal at a gate thereof, the first transistor being connected to a first voltage, a second transistor for receiving the input signal at a gate thereof, the second transistor being connected to a second voltage, a make-link type fuse serially linked between the first and second transistors by application of energy, and a sensing circuit, connected to the make-link type fuse, for sensing whether the make-link type fuse is linked between the first and second transistors or not and for outputting a control signal based on the sensed result and the input signal. The first and second transistors are complementarily connected to turn on one of the first and second transistors in response to the input signal, thereby preventing current from flowing between the first and second transistors when the make-link type fuse is linked between the first and second transistors.

Abstract: A fuse circuit according to the present invention includes fuse elements each connected to first and second nodes, a sense circuit for sensing a difference of currents flowing through the fuse elements, and an amplifier circuit for amplifying voltages of the first and second nodes with rail-to-rail voltages, respectively. By this configuration, the resistor difference of the fuse elements is sensed by a current difference, thus whether a fuse element is programmed is exactly sensed regardless of capacitive parasitic loading of the respective nodes.

Abstract: A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

Abstract: Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

Abstract: An input circuit having one or more individual signature circuits connected in parallel between an input line and an voltage node in a semiconductor device and an individual signature circuit are provided. The individual signature circuits are isolated from an input/output port to which a high frequency signal is applied so that the input/output port of the semiconductor device can operate at high speed. The signature circuits are provided for an input/output port to which a relatively low frequency signal is applied. An individual signature circuit includes an indexer and a selector connected in series between the voltage node and the input line. The selector includes two terminals which are electrically short-circuited or snapped in response to a control signal, and the indexer includes one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the voltage reducing devices.

Abstract: A semiconductor memory device and a method of generating a chip selection signal that enable the analysis of the causes of defects of defective memory devices selected by a user from a system with a plurality of memory devices and the fixing the defects are provided. The semiconductor memory device includes a programming register, an input buffer control circuit, and a chip selection circuit. The programming register activates an output signal in response to an address and a command input from the outside. The input buffer control circuit activates the plurality of data input buffer circuits in response to the output signal of the programming register. The chip selection circuit activates a defect detecting & repairing circuit, such as a repair circuit or a test time shortening circuit, when at least one of output signals of the plurality of data input buffer circuits is in a first logic state.

Abstract: A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

Abstract: A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

Abstract: A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

Abstract: Integrated circuit memory devices include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. A transistor in the first transmission part and a transistor in the first input/output selection part can share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part also can share a second common source/drain region. First and second input/output selection parts also may be provided between the first and second transmission parts. At least one sense amplifier part may be provided between the first and second input/output selection parts.

Abstract: A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation.

Abstract: A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation.

Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.