Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device, memory system and method of operating memory device
    Patent number: 9761315
    Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Doo-Hyun Kim, Dae-Seok Byeon, Chi-Weon Yoon
  • Memory devices and methods of operating the memory devices by programming normal cells after programming a first dummy cell
    Patent number: 9721664
    Abstract: A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wan Nam, Kyung-min Kang
  • Operating method of nonvolatile memory and method of controlling nonvolatile memory
    Patent number: 9704590
    Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kang-Bin Lee, Junghoon Park
  • NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20170194058
    Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: CHI WEON YOON, DONGHYUK CHAE, JAE-WOO PARK, SANG-WAN NAM
  • 3D flash memory device having different dummy word lines and data storage devices including same
    Patent number: 9697901
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kitae Park
  • MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING MEMORY DEVICE
    Publication number: 20170168742
    Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: SANG-WAN NAM, Doo-Hyun Kim, Dae-Seok Byeon, Chi-Weon Yoon
  • Nonvolatile memory devices and driving methods thereof
    Patent number: 9666283
    Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
  • Nonvolatile memory device and method of erasing nonvolatile memory device
    Patent number: 9659662
    Abstract: A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kang-Bin Lee, Kihwan Choi
  • Memory system and driving method thereof using at least two zone voltages
    Patent number: 9659660
    Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kuihan Ko, Yang-Lo Ahn, Kitae Park
  • NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    Publication number: 20170117048
    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: YOON-HEE CHOI, SANG-WAN NAM, KANG-BIN LEE
  • Nonvolatile memory device, operating method thereof and memory system including the same
    Patent number: 9627086
    Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Donghyuk Chae, Jae-Woo Park, Sang-Wan Nam
  • Nonvolatile memory device and erasing method thereof
    Patent number: 9627076
    Abstract: According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Nonvolatile memory device and method of operating the same
    Patent number: 9620232
    Abstract: According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Voltage generator and semiconductor memory device
    Patent number: 9601209
    Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyun Kim, Young-Sun Min, Sung-Whan Seo, Won-Tae Kim, Sang-Wan Nam
  • MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING MEMORY DEVICE
    Publication number: 20170069390
    Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: SANG-WAN NAM, DOO-HYUN KIM, DAE-SEOK BYEON, CHl-WEON YOON
  • Method of operating memory controller and data storage device including memory controller
    Patent number: 9588714
    Abstract: In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Kitae Park
  • Nonvolatile memory device and method of programming the same
    Patent number: 9564229
    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Sang-Wan Nam, Kang-Bin Lee
  • Nonvolatile memory and erasing method thereof
    Patent number: 9552884
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung, Junghoon Park
  • Memory system and method of driving memory system using zone voltages
    Patent number: 9552886
    Abstract: A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Minsu Kim, Kang-Bin Lee, Kitae Park
  • OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20160379716
    Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Inventors: Sang-Wan NAM, Kang-Bin LEE, Junghoon PARK