Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF
    Publication number: 20160365149
    Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 15, 2016
    Inventors: SANG-WAN NAM, Sun-Min Yun, Bongsoon Lim, Yoon-Hee Choi
  • NONVOLATILE MEMORY AND ERASING METHOD THEREOF
    Publication number: 20160358660
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventors: SANG-WAN NAM, WON-TAECK JUNG, JUNGHOON PARK
  • Memory device, memory system and method of operating memory device
    Patent number: 9514827
    Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Doo-Hyun Kim, Dae-Seok Byeon, Chi-Weon Yoon
  • Memory device and memory system
    Patent number: 9508441
    Abstract: A memory device includes a memory cell array including a plurality of NAND strings, wherein each of the NAND strings includes a ground selection transistor connected to a ground selection line, memory cells connected to word lines, and a string selection transistor connected to a string selection line, wherein the ground selection line, the word lines, and the string selection line are vertically stacked on a substrate. A control logic adjusts a ground selection line voltage applied to the ground selection line or a string selection line voltage applied to the string selection line to a negative level in at least a portion of a program section during which a program operation related to a memory cell selected from among the memory cells is performed.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: November 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Dae-Seok Byeon, Chi-Weon Yoon
  • NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    Publication number: 20160343443
    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: YOON-HEE CHOI, SANG-WAN NAM, KANG-BIN LEE
  • METHOD OF OPERATING MEMORY CONTROLLER AND DATA STORAGE DEVICE INCLUDING MEMORY CONTROLLER
    Publication number: 20160335027
    Abstract: In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan NAM, Kitae PARK
  • Three-dimensional flash memory device including dummy word line
    Patent number: 9496038
    Abstract: A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash memory includes a first dummy word line disposed between a ground selection line and a main word line, and a second dummy word line disposed between the main word line and a string selection line and being asymmetric with respect to the first dummy word line. Voltages of different levels are respectively applied to the first and second dummy word lines during a read operation.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghun Kwak, Sang-Wan Nam, Daeseok Byeon, Chiweon Yoon
  • 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME
    Publication number: 20160322107
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventors: SANG-WAN NAM, KITAE PARK
  • THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE
    Publication number: 20160314840
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 27, 2016
    Inventors: SANG-WAN NAM, WON-TAECK JUNG
  • Erase method of nonvolatile memory device and storage device employing the same
    Patent number: 9478296
    Abstract: A method of erasing a nonvolatile memory device which includes a plurality of memory blocks includes receiving an erase command; erasing a selected memory block among the plurality of memory blocks in response to the erase command; and performing an operation of checking whether a threshold voltage of a selection transistor connected to at least one selection line for selecting strings included in the selected memory block is changed while performing an erase verification operation for checking whether the selected memory block is normally erased.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 25, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Memory device and memory system including the same
    Patent number: 9478290
    Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 25, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Kyung-Hwa Kang, Dae-Seok Byeon, Chi-Weon Yoon
  • Operating method of nonvolatile memory and method of controlling nonvolatile memory
    Patent number: 9466387
    Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kang-Bin Lee, Junghoon Park
  • MEMORY SYSTEM AND DRIVING METHOD THEREOF
    Publication number: 20160284412
    Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan NAM, Kuihan KO, Yang-Lo AHN, Kitae PARK
  • Nonvolatile memory and erasing method thereof
    Patent number: 9449699
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung, Junghoon Park
  • NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF
    Publication number: 20160254054
    Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 1, 2016
    Inventors: Kyung-Hwa KANG, Sang-Wan NAM, Donghyuk CHAE, ChiWeon YOON
  • Erase system and method of nonvolatile memory device
    Patent number: 9431115
    Abstract: An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Wan Nam
  • Nonvolatile memory device and method of programming the same
    Patent number: 9424931
    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Sang-Wan Nam, Kang-Bin Lee
  • Nonvolatile memory device and programming method thereof
    Patent number: 9424932
    Abstract: A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Sang-Wan Nam, Kang-Bin Lee
  • Method of operating memory controller and data storage device including memory controller
    Patent number: 9418753
    Abstract: In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kitae Park
  • Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
    Patent number: 9418749
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung