Patents by Inventor Sang-Wan Nam

Sang-Wan Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20160232981
    Abstract: According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.
    Type: Application
    Filed: April 15, 2016
    Publication date: August 11, 2016
    Inventor: Sang-Wan NAM
  • Memory system and programming method thereof
    Patent number: 9396800
    Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Won Shim, Sang-Wan Nam, Kitae Park
  • Erase system and method of nonvolatile memory device
    Patent number: 9396802
    Abstract: An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Wan Nam
  • Nonvolatile memory device
    Patent number: 9391088
    Abstract: The nonvolatile memory device includes a plurality of memory cells being stacked in a direction perpendicular to a substrate. A string select transistor is connected between the memory cells and a bit line. A string select line is connected to the string select transistor. A one directional device is connected between the substrate and the string select line and configured to transmit a bias voltage from the substrate toward the string select line in an erase operation.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Memory system and driving method thereof
    Patent number: 9378828
    Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kuihan Ko, Yang-Lo Ahn, Kitae Park
  • Nonvolatile memory device and worldline driving method thereof
    Patent number: 9378820
    Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Sun-Min Yun, Bong-Soon Lim, Yoon-Hee Choi
  • NONVOLATILE MEMORY AND ERASING METHOD THEREOF
    Publication number: 20160148698
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Inventors: SANG-WAN NAM, WON-TAECK JUNG, JUNGHOON PARK
  • Nonvolatile memory devices and driving methods thereof
    Patent number: 9349455
    Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
  • NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20160118133
    Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
    Type: Application
    Filed: July 28, 2015
    Publication date: April 28, 2016
    Inventors: CHI WEON YOON, DONGHYUK CHAE, JAE-WOO PARK, SANG-WAN NAM
  • Nonvolatile memory device and method of operating the same
    Patent number: 9318202
    Abstract: According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Nonvolatile memory device and method of operating the same
    Patent number: 9312008
    Abstract: According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • Memory system including nonvolatile memory device and erase method thereof
    Patent number: 9293206
    Abstract: An erase method of a three-dimensional nonvolatile memory device may include receiving an erase command, applying an erase voltage to perform an erase operation to a selected memory region in response to the erase command, suspending the erase operation by cutting off the erase voltage after a specific time has elapsed from when the erase voltage is applied, receiving a resume command after a reference time has elapsed from when the erase operation is suspended, and applying the erase voltage to the memory region for the specific time according to the resume command.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wan Nam
  • 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME
    Publication number: 20160071592
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: SANG-WAN NAM, KITAE PARK
  • Nonvolatile memory and erasing method thereof
    Patent number: 9281070
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung, Junghoon Park
  • NONVOLATILE MEMORY DEVICE
    Publication number: 20160064388
    Abstract: The nonvolatile memory device includes a plurality of memory cells being stacked in a direction perpendicular to a substrate. A string select transistor is connected between the memory cells and a bit line. A string select line is connected to the string select transistor. A one directional device is connected between the substrate and the string select line and configured to transmit a bias voltage from the substrate toward the string select line in an erase operation.
    Type: Application
    Filed: March 31, 2015
    Publication date: March 3, 2016
    Inventor: SANG-WAN NAM
  • NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    Publication number: 20160064083
    Abstract: A nonvolatile memory device of the inventive concept includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line.
    Type: Application
    Filed: June 8, 2015
    Publication date: March 3, 2016
    Inventors: SANG-WAN NAM, WANDONG KIM
  • MEMORY SYSTEM AND DRIVING METHOD THEREOF
    Publication number: 20160055914
    Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
    Type: Application
    Filed: November 4, 2015
    Publication date: February 25, 2016
    Inventors: Sang-Wan NAM, Kuihan KO, Yang-Lo AHN, Kitae PARK
  • NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF
    Publication number: 20160042792
    Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
  • NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF
    Publication number: 20160035423
    Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.
    Type: Application
    Filed: June 16, 2015
    Publication date: February 4, 2016
    Inventors: Sang-Wan NAM, Sun-Min YUN, Bongsoon LIM, Yoon-Hee CHOI
  • THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE
    Publication number: 20160035431
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: SANG-WAN NAM, WON-TAECK JUNG