Patents by Inventor Sang Won Park

Sang Won Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11002797
    Abstract: The fault diagnosis circuit includes a first line including a first resistor, having one end connected to the positive (+) terminal of a battery, and having the other end connected to a first input unit of an analog to digital converter (ADC); a second line including a second resistor, having one end connected to the positive (+) terminal of the battery, and having the other end connected to a first input unit of a comparator; and a third line including a third resistor, having one end connected to the negative (?) terminal of the battery, having a first other end connected to a second input unit of the ADC, and having a second other end connected to a second input unit of the comparator. A fault in a battery management system can be efficiently diagnosed using a smaller number of elements.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Jae-Seong Park, Seulkirom Kim, Jae-Min Park, Yeong-Geun Yeo, Sang-Ho Lee, Jong-Won Choi
  • Publication number: 20210132719
    Abstract: A display device includes a display including a plurality of pixels and an input sensor for sensing an input of a user. The display device includes: a driving controller for providing the display with a scan signal and a data signal according to a driving frequency; an input controller for providing a touch driving signal to the input sensor; a horizontal synchronization signal information line connecting the driving controller and the input controller, the horizontal synchronization signal information line transmitting a horizontal synchronization signal therethrough; and a vertical synchronization signal information line connecting the driving controller and the input controller, the vertical synchronization signal information line transmitting a vertical synchronization signal therethrough. Amplitude of the vertical synchronization signal or the horizontal synchronization signal varies according to the driving frequency.
    Type: Application
    Filed: June 19, 2020
    Publication date: May 6, 2021
    Inventors: Sang Hun PARK, Soo Won KIM, Il Ho LEE
  • Publication number: 20210118587
    Abstract: The present invention relates to a radioactive chemical waste treatment apparatus including an adsorption unit including an radioactive chemical waste adsorption member for adsorbing and separating radioactive chemical wastes from radioactive chemical waste-containing fluid, and a regeneration unit which is in fluidic communication with the adsorption unit and is for regenerating the radioactive chemical waste adsorption member by desorbing the radioactive chemical wastes from the adsorption member with the radioactive chemical wastes adsorbed thereonto, and to a radioactive chemical waste treatment method including (A) adsorbing radioactive chemical wastes onto a radioactive chemical waste adsorption member and separating the radioactive chemical wastes from a radioactive chemical waste-containing fluid, and (B) desorbing the radioactive chemical wastes from the radioactive chemical waste adsorption member with the radioactive chemical wastes adsorbed thereonto, and regenerating the radioactive chemical wast
    Type: Application
    Filed: October 14, 2020
    Publication date: April 22, 2021
    Inventors: Sang Eun BAE, Hwa Kyeung JEONG, Dong Woo LEE, Tae Hong PARK, Jei Won YEON, Kun Ho CHUNG, Sang Ho LIM, Jai Il PARK, Wan Sik CHA, Byung Man KANG
  • Publication number: 20210112870
    Abstract: An aerosol generating device includes an accommodator for accommodating a cigarette through an opening formed at an end of the accommodator, a first susceptor located in the accommodator, a second susceptor disposed a predetermined distance away from the first susceptor, a coil that generates an alternating magnetic field for the first and second susceptors to generate heat, and a temperature sensor arranged proximate to the second susceptor to measure a temperature profile of the second susceptor. The temperature profile of the second susceptor corresponds to a temperature profile of the first susceptor, and a temperature of the first susceptor is determined based on the temperature profile of the second susceptor.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 22, 2021
    Applicant: KT&G CORPORATION
    Inventors: Sang Kyu PARK, Seung Won LEE, Jong Sub LEE
  • Publication number: 20210027840
    Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.
    Type: Application
    Filed: March 18, 2020
    Publication date: January 28, 2021
    Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
  • Publication number: 20210027841
    Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.
    Type: Application
    Filed: August 12, 2020
    Publication date: January 28, 2021
    Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
  • Publication number: 20210005629
    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI
  • Publication number: 20200411103
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
  • Patent number: 10804293
    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Sang-Wan Nam, Bong-Soon Lim
  • Publication number: 20200312379
    Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.
    Type: Application
    Filed: October 2, 2019
    Publication date: October 1, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Hojoon Kim, Sang-won Park, Sang-won Shim, Wonbo Shim
  • Publication number: 20200303011
    Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.
    Type: Application
    Filed: November 25, 2019
    Publication date: September 24, 2020
    Inventors: Sang-Won PARK, Won Bo SHIM, Bong Soon LIM
  • Publication number: 20200243140
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
  • Patent number: 10712955
    Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-chang Jeon, Sang-won Park, Dong-kyo Shim, Dong-hun Kwak
  • Patent number: 10699782
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Publication number: 20200168547
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 28, 2020
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI
  • Patent number: 10658040
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Publication number: 20200135758
    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.
    Type: Application
    Filed: June 13, 2019
    Publication date: April 30, 2020
    Inventors: Sang-Won PARK, Sang-Wan NAM, Bong-Soon LIM
  • Publication number: 20200126980
    Abstract: Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.
    Type: Application
    Filed: March 5, 2017
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Sang-Won Park, Dennis G. Hanken, Sishir Bhowmick, Leonard C. Pipes
  • Patent number: 10622091
    Abstract: A nonvolatile memory device includes a memory cell array and a bad block remapping circuit. The memory cell array includes a first mat and a second mat that are paired with each other. The first mat includes a plurality of first memory blocks. The second mat includes a plurality of second memory blocks. A first selection memory block among the plurality of first memory blocks and a second selection memory block among the plurality of second memory blocks are accessed based on a first address. The bad block remapping circuit generates a first remapping address based on the first address when it is determined that the first selection memory block is defective. A first remapping memory block among the plurality of first memory blocks and the second selection memory block are accessed based on the first remapping address.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Lee, Bong-Soon Lim, Sang-Won Park
  • Patent number: 10604894
    Abstract: The present invention provides a method of carbonating carbon dioxide with high purity using a paper mill waste sludge by preparing a paper mill waste sludge which is a waste product discharged during the production of papermaking, adding acid to the paper mill waste sludge and reacting the acid therewith to produce a mixed solution and stirring, separating a supernatant of the mixed solution into an eluate, adding a basic substance to the eluate and adjusting pH to precipitate some of the ions in the eluate, and then adding a reaction initiator to the eluate in which some ions are precipitated and removed, and injecting carbon dioxide for a carbonation reaction.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 31, 2020
    Assignee: Korea Institute of Geoscience and Mineral Resources
    Inventors: Chi-Wan Jeon, Sang-Won Park, Jun-Hwan Bang, Kyung-Sun Song, Seung-Woo Lee, Hwan-Ju Jo