Abstract: An example electronic device includes a housing; a touchscreen display; a microphone; at least one speaker; a button disposed on a portion of the housing or set to be displayed on the touchscreen display; a wireless communication circuit; a processor; and a memory. When a user interface is not displayed on the touchscreen display, the electronic device enables a user to receive a user input through the button, receives user speech through the microphone, and then provides data on the user speech to an external server. An instruction for performing a task is received from the server. When the user interface is displayed on the touchscreen display, the electronic device enables the user to receive the user input through the button, receives user speech through the microphone, and then provides data on the user speech to the external server.

Abstract: A battery module includes at least one cell assembly including a plurality of secondary batteries, a gas pipe configured to allow gas produced in a module housing to move therein, and the module housing including a lower case having one open side and an internal space in which the at least one cell assembly is received, and an upper case coupled to one side of the lower case to cover the one open side of the lower case and having a receiving space in which the gas pipe is received, and a connection hole to which one end of the gas pipe is connected such that the gas pipe and the internal space are in communication with each other.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

Abstract: Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

Abstract: The disclosure relates to a semiconductor memory device including a semiconductor memory module and a semiconductor memory control unit, and since the semiconductor memory module includes a power management unit, and the power management unit generates a reference voltage and various internal voltages to be supplied to a dynamic random access memory (DRAM) chip array, and receives the internal voltages supplied to the DRAM chip array by feedback to measure and compensate the internal voltages, a stable and accurate voltage can be supplied to the DRAM chip array.

Abstract: Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

Abstract: A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Abstract: A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Abstract: A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Abstract: A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

Abstract: A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.