Patents by Inventor Sanjeev Aggarwal

Sanjeev Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10103197
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 16, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 10079339
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 18, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 10062839
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 28, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 10056544
    Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers and then depositing additional encapsulating material prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 21, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • Publication number: 20180158498
    Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev AGGARWAL, Sarin A. Deshpande, Jon Slaughter
  • Publication number: 20180145248
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 24, 2018
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Publication number: 20180130944
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 10, 2018
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20180123032
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9893275
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: February 13, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9893274
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 13, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20180033959
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 9865804
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure, through the second tunnel barrier layer to form a second tunnel barrier and provide sidewalls thereof and the second layer of ferromagnetic material to provide sidewalls thereof. Thereafter, etching, through the first tunnel barrier layer to form a first tunnel barrier to provide sidewalls thereof and etching the first layer of ferromagnetic material to provide sidewalls thereof. The process may then include oxidizing the sidewalls of (i) the first tunnel barrier and (ii) the first layer of ferromagnetic material.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 9, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 9837603
    Abstract: Encapsulation of the magnetoresistive device after formation protects the sidewalls of the magnetoresistive device from degradation during subsequent deposition of interlayer dielectric material. The encapsulation also helps prevent short circuits between the top electrode of the magnetoresistive device and underlying layers within the magnetoresistive device. The encapsulation can be accomplished by depositing a layer of encapsulating material after device formation, where an etch back operation selectively removes the portions of the layer of encapsulating material other than the material on the sidewalls of the magnetoresistive device.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 5, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Publication number: 20170301857
    Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers and then depositing additional encapsulating material prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Applicant: Everspin Technologies, Inc.
    Inventors: Chaitanya MUDIVARTHI, Sarin A. DESHPANDE, Sanjeev AGGARWAL
  • Patent number: 9793470
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching (i) the first encapsulation layer which is disposed over the exposed surface of the dielectric layer and (ii) re-deposited material disposed on the dielectric layer, wherein, thereafter a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region. The method further includes depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer; and etching the remaining layers of the stack/structure (via one or more etch processes).
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Publication number: 20170288136
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure, through the second tunnel barrier layer to form a second tunnel barrier and provide sidewalls thereof and the second layer of ferromagnetic material to provide sidewalls thereof. Thereafter, etching, through the first tunnel barrier layer to form a first tunnel barrier to provide sidewalls thereof and etching the first layer of ferromagnetic material to provide sidewalls thereof. The process may then include oxidizing the sidewalls of (i) the first tunnel barrier and (ii) the first layer of ferromagnetic material.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 9728583
    Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 8, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Moazzem Hossain, Nicholas Rizzo
  • Patent number: 9722174
    Abstract: By manufacturing magnetoresistive devices using low-k dielectric materials as the inter-layer dielectrics and higher-k dielectric materials for hard masks and encapsulation, the overall dielectric constant characteristics of the magnetoresistive devices can be kept lower, thereby decreasing capacitance and allowing for higher speed operations. Elimination or reduction of residual higher-k dielectric material through stripping or other processes minimizes “islands” of higher-k dielectric material that can detract from overall dielectric constant performance. One or more masking and one or more etching steps can be used to form the devices either with or without the additional stripping of the higher-k material.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 1, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal
  • Patent number: 9722176
    Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: August 1, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • Patent number: 9711566
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: August 6, 2016
    Date of Patent: July 18, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande