Patents by Inventor Sanjeev Aggarwal

Sanjeev Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9343661
    Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 17, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Sanjeev Aggarwal, Chaitanya Mudivarthi
  • Publication number: 20160126454
    Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Application
    Filed: January 8, 2016
    Publication date: May 5, 2016
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • Publication number: 20160104835
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a ā€œZā€ axis magnetic field onto sensors orientated in the XY plane.
    Type: Application
    Filed: November 30, 2015
    Publication date: April 14, 2016
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu WHIG, Phillip MATHER, Kenneth SMITH, Sanjeev AGGARWAL, Jon SLAUGHTER, Nicholas RIZZO
  • Patent number: 9306157
    Abstract: A method of manufacturing a magnetoresistive-based device using a plurality of hard masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second hard mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second hard mask to form, and a second electrode.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 5, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Patent number: 9281168
    Abstract: The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: March 8, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Chaitanya Mudivarthi, Jason Allen Janesky, Jijun Sun, Frederick Bennett Mancoff, Sanjeev Aggarwal
  • Patent number: 9269894
    Abstract: Isolation of magnetic layers in the magnetoresistive stack is achieved by passivation of sidewalls of the magnetic layers or deposition of a thin film of non-magnetic dielectric material on the sidewalls prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: February 23, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • Patent number: 9269891
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a ā€œZā€ axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 23, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20160027998
    Abstract: A via underlying a magnetoresistive device is formed to include a lower portion that includes a first material and an upper portion that includes a second material, where the second material is part of the material making up the bottom electrode of the magnetoresistive device. The via is formed by partially filling a via hole with the first material and then filling the remaining portion of the via hole when a layer of the second material is deposited to form the basis for the bottom electrode. The layer of second material is polished to provide a planar surface on which to form the magnetoresistive stack and top electrode. After forming the magnetoresistive stack and top electrode, the layer of second material is etched to form the bottom electrode. Such a via allows the magnetoresistive stack to be formed directly over the via, thereby reducing the area required for each device and increasing density in applications such as MRAMs.
    Type: Application
    Filed: July 24, 2014
    Publication date: January 28, 2016
    Inventors: Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Publication number: 20150380640
    Abstract: A method of manufacturing a magnetoresistive-based device using a plurality of hard masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second hard mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second hard mask to form, and a second electrode.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Sarin Deshpande, Sanjeev Aggarwal
  • Publication number: 20150357559
    Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Moazzem Hossain, Nicholas Rizzo
  • Publication number: 20150357560
    Abstract: The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Chaitanya Mudivarthi, Jason Allen Janesky, Jijun Sun, Frederick Bennett Mancoff, Sanjeev Aggarwal
  • Publication number: 20150318465
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Application
    Filed: July 12, 2015
    Publication date: November 5, 2015
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9166155
    Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: October 20, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Publication number: 20150236254
    Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Publication number: 20150236249
    Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
    Type: Application
    Filed: June 4, 2014
    Publication date: August 20, 2015
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Sanjeev Aggarwal, Chaitanya Mudivarthi
  • Publication number: 20150236248
    Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The level of isotropy is different for each of the two etching steps, thereby providing advantages associated with isotropic etching as well as more anisotropic etching. The level of isotropy is controlled by varying power and pressure during plasma etching operations.
    Type: Application
    Filed: June 4, 2014
    Publication date: August 20, 2015
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel, Nicholas Rizzo, Jason Allen Janesky
  • Publication number: 20150236250
    Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The etching chemistries are different for each of the two etching steps. The first chemistry used to etch the top portion of the electrode is more selective with respect to the conductive material of the top electrode, thereby reducing unwanted erosion of the photoresist and hard mask layers. The second chemistry is less corrosive than the first chemistry and does not damage the layers underlying the top electrode, such as those included in the magnetic tunnel junction.
    Type: Application
    Filed: September 22, 2014
    Publication date: August 20, 2015
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 9093640
    Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 28, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9054297
    Abstract: A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F2, and a uniform thickness of material between the bit lines and the underlying memory elements.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 9, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Patent number: 9023219
    Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin Deshpande, Sanjeev Aggarwal, Kerry Nagel