Patents by Inventor Sanjeev Aggarwal

Sanjeev Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ISOLATION OF MAGNETIC LAYERS DURING ETCH IN A MAGNETORESISTIVE DEVICE
    Publication number: 20150102006
    Abstract: Isolation of magnetic layers in the magnetoresistive stack is achieved by passivation of sidewalls of the magnetic layers or deposition of a thin film of non-magnetic dielectric material on the sidewalls prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Application
    Filed: June 4, 2014
    Publication date: April 16, 2015
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE
    Publication number: 20150079699
    Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
    Type: Application
    Filed: November 4, 2014
    Publication date: March 19, 2015
    Inventors: Sarin Deshpande, Sanjeev Aggarwal, Kerry Nagel
  • Method of manufacturing a magnetoresistive-based device with via integration
    Patent number: 8877522
    Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 4, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Kerry Nagel, Sarin Deshpande, Moazzem Hossain, Sanjeev Aggarwal
  • METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE
    Publication number: 20140315329
    Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 23, 2014
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE WITH VIA INTEGRATION
    Publication number: 20140287536
    Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.
    Type: Application
    Filed: May 21, 2014
    Publication date: September 25, 2014
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Nagel, Sarin Deshpande, Moazzem Hossain, Sanjeev Aggarwal
  • METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS
    Publication number: 20140220707
    Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
    Type: Application
    Filed: March 19, 2014
    Publication date: August 7, 2014
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE
    Publication number: 20140212993
    Abstract: A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber.
    Type: Application
    Filed: January 31, 2014
    Publication date: July 31, 2014
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Method of manufacturing a magnetoresistive-based device with via integration
    Patent number: 8790935
    Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 29, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Kerry Nagel, Sarin Deshpande, Moazzern Hossain, Sanjeev Aggarwal
  • Method of manufacturing a magnetoresistive-based device
    Patent number: 8747680
    Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 10, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR
    Publication number: 20140138346
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Application
    Filed: August 21, 2013
    Publication date: May 22, 2014
    Applicant: EverSpin Technologies, Inc.
    Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Method for manufacturing and magnetic devices having double tunnel barriers
    Patent number: 8685756
    Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 1, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Process integration of a single chip three axis magnetic field sensor
    Patent number: 8518734
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: August 27, 2013
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Voltage-controlled oscillator module having adjustable oscillator gain and related operating methods
    Patent number: 8451064
    Abstract: Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sanjeev Maheshwari, Emerson Fang, Sanjeev Aggarwal
  • METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS
    Publication number: 20130082339
    Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Electronic device including a magneto-resistive memory device and a process for forming the electronic device
    Patent number: 8236578
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: August 7, 2012
    Assignee: Everspin Technologies, Inc.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • Properties of metallic copper diffusion barriers through silicon surface treatments
    Patent number: 8211794
    Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: July 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Valli Arunachalam, Satyavolu Srinivas Papa Rao, Sanjeev Aggarwal, Stephan Grunow
  • MAGNETIC RANDOM ACCESS MEMORY INTEGRATION HAVING IMPROVED SCALING
    Publication number: 20120156806
    Abstract: A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F2, and a uniform thickness of material between the bit lines and the underlying memory elements.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 21, 2012
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Kerry Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
    Publication number: 20120122247
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • VOLTAGE-CONTROLLED OSCILLATOR MODULE HAVING ADJUSTABLE OSCILLATOR GAIN AND RELATED OPERATING METHODS
    Publication number: 20120086482
    Abstract: Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sanjeev MAHESHWARI, Emerson FANG, Sanjeev AGGARWAL
  • Electronic device including a magneto-resistive memory device and a process for forming the electronic device
    Patent number: 8119424
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 21, 2012
    Assignee: Everspin Technologies, Inc.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo