Patents by Inventor Saravanan Sethuraman

Saravanan Sethuraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data buffer spare architectures for dual channel serial interface memories
    Patent number: 9904611
    Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
  • Concurrent upgrade and backup of non-volatile memory
    Patent number: 9886200
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • Delaying programming requests in flash memory
    Patent number: 9875034
    Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: January 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Saravanan Sethuraman, Gary A Tressler, Harish Venkataraman
  • Concurrent upgrade and backup of non-volatile memory
    Patent number: 9875036
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • System for securing contents of removable memory
    Patent number: 9858208
    Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright
  • REFERENCE VOLTAGE CALIBRATION IN MEMORY DURING RUNTIME
    Publication number: 20170358369
    Abstract: Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Diyanesh B. CHINNAKKONDA VIDYAPOORNACHARY, Edgar R. CORDERO, Stephen P. GLANCY, Jeremy R. NEATON, Saravanan SETHURAMAN
  • Method and apparatus for cache memory data processing
    Patent number: 9792209
    Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
  • PARALLEL READ AND WRITES IN 3D FLASH MEMORY
    Publication number: 20170293436
    Abstract: Embodiments herein describe a 3D flash memory system that includes multiple blocks where each block contains multiple pages arranged in a vertical stack. Instead of having a single command line indicating whether a read or program is to be performed, separate command lines are coupled to each of the blocks. As a result, if the memory system identifies a read request and a program request to different blocks, the requests can be performed in parallel. In one embodiment, a program command line is used to perform a program request on a first block while a read command line is used to perform a read request on a second block in the 3D flash memory system in parallel. Furthermore, because a program request can take much longer to complete than a read request, the 3D flash memory system can perform multiple read requests in parallel with the program request.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Saravanan SETHURAMAN, Gary A. TRESSLER, Harish VENKATARAMAN
  • SYSTEM AND METHOD FOR CONSERVING ENERGY IN NON-VOLATILE DUAL INLINE MEMORY MODULES
    Publication number: 20170293343
    Abstract: A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • DELAYING PROGRAMMING REQUESTS IN FLASH MEMORY
    Publication number: 20170293425
    Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Saravanan SETHURAMAN, Gary A. TRESSLER, Harish VENKATARAMAN
  • Thermal-aware memory
    Patent number: 9761294
    Abstract: A method for operating a memory system comprises receiving a write request associate with data, decoding an address of the write request, receiving thermal data indicating a temperature at the address of the write request, determining whether the temperature is above a threshold temperature, and writing the data to the address responsive to determining that the temperature is not above the threshold temperature.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Saravanan Sethuraman
  • Thermal-aware memory
    Patent number: 9734885
    Abstract: A method for operating a memory system includes receiving thermal data indicating a temperature at addresses in a memory array, and a write request associate with data. An address of the write request is decoded. It is determined whether a temperature at the address of the write request is above a threshold temperature. The data is sent to a short latency write queue responsive to determining that the temperature is not above the threshold temperature.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Saravanan Sethuraman
  • Method and apparatus for cache memory data processing
    Patent number: 9710381
    Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
  • CONCURRENT UPGRADE AND BACKUP OF NON-VOLATILE MEMORY
    Publication number: 20170160956
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 8, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • CONCURRENT UPGRADE AND BACKUP OF NON-VOLATILE MEMORY
    Publication number: 20170160937
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Application
    Filed: January 12, 2017
    Publication date: June 8, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • CONCURRENT UPGRADE AND BACKUP OF NON-VOLATILE MEMORY
    Publication number: 20170160936
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Application
    Filed: January 12, 2017
    Publication date: June 8, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • Reconfigurable power distribution system for three-dimensional integrated circuits
    Patent number: 9665115
    Abstract: A three-dimensional (3D) integrated circuit (IC) device can include a first die having a first supply line and a second die having a second supply line, a power header, and a voltage selection logic. The power header can be connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic can be connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vijay A. Mathiyalagan, Siva Rama K. Pullelli, Saravanan Sethuraman, Kenneth L. Wright
  • EFFICIENT CONFIGURATION OF MEMORY COMPONENTS
    Publication number: 20170090804
    Abstract: In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: John S. Bialas, JR., Stephen P. Glancy, Saravanan Sethuraman, Jacob D. Sloat
  • Detecting defective connections in stacked memory devices
    Patent number: 9607716
    Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 28, 2017
    Assignee: Internatiional Business Machines Corporation
    Inventors: Charles A. Kilmer, Warren E. Maule, Saravanan Sethuraman
  • Read distribution in a three-dimensional stacked memory based on thermal profiles
    Patent number: 9575671
    Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman, Kenneth L. Wright