Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: An apparatus for distributing plasma products includes first and second electrodes that each include planar surfaces. The first electrode forms first apertures from a first planar surface to a second planar surface; the second electrode forms second apertures from the third planar surface to the fourth planar surface. The electrodes couple through one or more adjustable couplers such that the third planar surface is disposed adjacent to the second planar surface with a gap therebetween, the gap having a gap distance. Each of the adjustable couplers has a range of adjustment. The first and second apertures are arranged such that for at least one position within the ranges of adjustment, none of the first apertures aligns with any of the second apertures to form an open straight-line path extending through both the first and second electrodes, and the gap distance is between 0.005 inch and 0.050 inch.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: Exemplary semiconductor showerheads may include a first plate characterized by a first surface in which a plurality of first apertures are defined, and further characterized by a second surface opposite the first surface and from which extends a plurality of annular members. Each annular member of the plurality of annular members may extend from a separate first aperture of the plurality of first apertures. A channel may be defined by each first aperture and corresponding annular member. The showerheads may also include a second plate coupled with the first plate and characterized by a first surface facing the first plate and a second surface opposite the first surface. A plurality of second apertures may be defined through the second plate within an internal area of the second plate. Each annular member of the plurality of annular members may extend within a separate second aperture of the plurality of second apertures.

Abstract: Exemplary etching methods may include flowing a hydrogen-containing precursor into a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into a remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma of the fluorine-containing precursor in the remote plasma region. The methods may include etching a pre-determined amount of a silicon-containing material from a substrate in a processing region of the semiconductor processing chamber. The methods may include measuring a radical density within the remote plasma region during the etching. The methods may also include halting the flow of the hydrogen-containing precursor into the semiconductor processing chamber when the radical density measured over time correlates to a produced amount of etchant to remove the pre-determined amount of the silicon-containing material.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: An apparatus for distributing plasma products includes first and second electrodes that each include planar surfaces. The first electrode forms first apertures from a first planar surface to a second planar surface; the second electrode forms second apertures from the third planar surface to the fourth planar surface. The electrodes couple through one or more adjustable couplers such that the third planar surface is disposed adjacent to the second planar surface with a gap therebetween, the gap having a gap distance. Each of the adjustable couplers has a range of adjustment. The first and second apertures are arranged such that for at least one position within the ranges of adjustment, none of the first apertures aligns with any of the second apertures to form an open straight-line path extending through both the first and second electrodes, and the gap distance is between 0.005 inch and 0.050 inch.

Abstract: Systems and methods may be used to produce coated components. Exemplary chamber components may include an aluminum, stainless steel, or nickel plate defining a plurality of apertures. The plate may include a hybrid coating, and the hybrid coating may include a first layer comprising a corrosion resistant coating. The first layer may extend conformally through each aperture of the plurality of apertures. The hybrid coating may also include a second layer comprising an erosion resistant coating extending across a plasma-facing surface of the semiconductor chamber component.

Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

Abstract: Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: Embodiments of the disclosure relate to a multi-plate faceplate having a first plate and a second plate. The first plate has a plurality of first plate openings. The second plate has a first surface, an opposed second surface and a plurality of second plate openings extending therethrough. The first surface is mechanically coupled to the first plate. A second plate opening has a conical portion configured to be fluidly coupled to a first plate opening and decreasing in cross-section in the depth direction thereof from the second surface. A surface of the conical portion is coated with a protective coating adjacent to the first and second surfaces. In another embodiment, the first plate has a protrusion extending therefrom into a recess formed inwardly of the first surface. The protrusion has a passage extending therethrough fluidly connected to the recess, which is fluidly connected to the second plate opening.

Abstract: Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: The present disclosure generally relates to apparatuses and methods for reducing particle contamination on substrate surfaces. In one example, the apparatus is embodied as a load lock chamber including a top heater liner disposed over and coupled to a heater pedestal. The top heater liner generally includes a top plate and one or more walls, which support the top heater liner over the heater pedestal. Since the top heater liner is in contact with the heater pedestal, the top heater liner is generally heated to a temperature at which contaminating particles are volatile, such as greater than about 100° C. In operation, volatile fluorine passing through or adjacent to the hot top heater liner remains in gaseous form and thus are pumped out of the load lock chamber. The top heater liner thus advantageously reduces the potential for contaminating particles depositing on the substrate surface and improves overall production yield.

Abstract: The present disclosure provides a substrate support assembly includes a substrate pedestal having an upper surface for receiving and supporting a substrate, a cover plate disposed on the substrate support pedestal, and two or more lift pins movably disposed through the substrate support pedestal and the cover plate. The cover plate includes a disk body having a central opening. The two or more lift pins are self supportive. Each of the two or more lift pins comprises one or more contact pads, and the contact pads of the lift pins extend into to the central opening of the cover plate to receive and support a substrate at an edge region of the substrate.

Abstract: An electrode having a first portion and a second portion is formed over a substrate to couple to a bias RF power. The first portion is configured to compensate for an electric field at the second portion to even out a distribution of an etching strength over a workpiece placed over the electrode.

Abstract: A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material.

Abstract: In some embodiments, a gas distribution apparatus may include: a manifold having a gas inlet to receive a process gas from a fast gas exchange unit and a first gas outlet to provide the process gas to a first gas delivery zone; a plurality of flow restrictors fluidly coupled to one another in parallel and to the gas inlet, wherein each of the plurality of flow restrictors are configured to allow at least a portion of a total flow of a process gas through each of the plurality of flow restrictors; and a plurality of valves each coupled to respective ones of the plurality of flow restrictors, wherein the plurality of valves are configured to be selectively opened to allow the process gas to flow through selective ones of the plurality of flow restrictors to provide a desired percentage of a total flow of the process gas to the outlet.