Patents by Inventor Saravuth Sirinorakul
Saravuth Sirinorakul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9805955Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.Type: GrantFiled: November 9, 2016Date of Patent: October 31, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
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Patent number: 9773722Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).Type: GrantFiled: May 7, 2015Date of Patent: September 26, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjavasukul
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Patent number: 9761435Abstract: A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound.Type: GrantFiled: September 4, 2008Date of Patent: September 12, 2017Assignee: UTAC THAI LIMITEDInventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
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Patent number: 9741642Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.Type: GrantFiled: February 11, 2016Date of Patent: August 22, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjasukul
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Patent number: 9711343Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.Type: GrantFiled: December 14, 2007Date of Patent: July 18, 2017Assignee: UTAC THAI LIMITEDInventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
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Patent number: 9564387Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.Type: GrantFiled: July 8, 2015Date of Patent: February 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Antonio Bambalan Dimaano, Jr., Rui Huang
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Publication number: 20160300786Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.Type: ApplicationFiled: June 17, 2016Publication date: October 13, 2016Applicant: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Publication number: 20160300783Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.Type: ApplicationFiled: June 17, 2016Publication date: October 13, 2016Applicant: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Publication number: 20160293533Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.Type: ApplicationFiled: June 17, 2016Publication date: October 6, 2016Applicant: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Patent number: 9449905Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.Type: GrantFiled: March 26, 2013Date of Patent: September 20, 2016Assignee: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Patent number: 9449900Abstract: A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector bumps of the die after reflowing. In some embodiments, the support features are formed from material that is different from the leadframe, such as by a ball drop process or a plating process. In some embodiments, the support features are formed from the leadframe material, such as by etching. In some embodiments, the support features are covered with a coating material.Type: GrantFiled: July 12, 2010Date of Patent: September 20, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
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Publication number: 20160240460Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.Type: ApplicationFiled: April 26, 2016Publication date: August 18, 2016Applicant: UTAC Thai LimitedInventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
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Patent number: 9397031Abstract: Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor packages into a molding device, adding a molding material on a surface of the leadframe, molding the molding material, such that the molding material covers the entire surface of the semiconductor packages except conducting terminals, and singulating the semiconductor packages from the leadframe after molding the molding material.Type: GrantFiled: November 29, 2012Date of Patent: July 19, 2016Assignee: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Publication number: 20160172282Abstract: Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor packages into a molding device, adding a molding material on a surface of the leadframe, molding the molding material, such that the molding material covers the entire surface of the semiconductor packages except conducting terminals, and singulating the semiconductor packages from the leadframe after molding the molding material.Type: ApplicationFiled: November 29, 2012Publication date: June 16, 2016Applicant: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Patent number: 9355940Abstract: A semiconductor package comprises a die attach pad and an auxiliary support member at least partially circumscribing the die attach pad. A set of contact leads is formed extending outward from the die attach pad. A first set of contact pads is formed on the bottom surface of the distal ends of the contact leads. An optional second set of contact pads is formed at the bottom surface of the proximal end. The auxiliary support member prevents damage to the contact leads and prevents the leads from bending during the manufacturing process.Type: GrantFiled: December 10, 2012Date of Patent: May 31, 2016Assignee: UTAC THAI LIMITEDInventor: Saravuth Sirinorakul
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Patent number: 9349679Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.Type: GrantFiled: August 19, 2011Date of Patent: May 24, 2016Assignee: UTAC THAI LIMITEDInventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
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Publication number: 20160064310Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.Type: ApplicationFiled: July 8, 2015Publication date: March 3, 2016Inventors: Saravuth Sirinorakul, Antonio Bambalan Dimaano, Jr., Rui Huang
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Patent number: 9196470Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.Type: GrantFiled: February 10, 2009Date of Patent: November 24, 2015Assignee: UTAC THAI LIMITEDInventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
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Patent number: 9196504Abstract: Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts.Type: GrantFiled: July 3, 2012Date of Patent: November 24, 2015Assignee: UTAC DONGGUAN LTD.Inventors: Albert Loh, Edward Then, Serafin Pedron, Jr., Saravuth Sirinorakul
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Patent number: 9099294Abstract: A process for forming an optical package comprises at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, mounting at least one optical semiconductor device on the molded leadframe strip, at least partially encasing the molded leadframe strip, and singulating the molded leadframe strip to form discrete packages for optical applications. An apparatus for forming an optical package comprises means for at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one optical semiconductor device on the at least one molded leadframe strip, means for at least partially encasing the molded leadframe strip, and means for singulating the molded leadframe strip to form discrete and grid array packages.Type: GrantFiled: October 9, 2009Date of Patent: August 4, 2015Assignee: UTAC Thai LimitedInventors: Somchai Nondhasitthichai, Saravuth Sirinorakul