Abstract: A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Abstract: A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a memory cell array having a plurality of normal signal lines for selecting a memory cell, a redundant cell array including three or more of odd number of spare signal lines for compensating for defectiveness in the memory cell array, a decoder for decoding an address signal to select a normal signal line, a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line, and a test control circuit for controlling the decoder and the spare decoder to perform a test of applying voltage between adjacent signal lines in the normal signal lines and the spare signal lines.

Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Abstract: A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output o an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches-an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a memory cell array having a plurality of normal signal lines for selecting a memory cell, a redundant cell array including three or more of odd number of spare signal lines for compensating for defectiveness in the memory cell array, a decoder for decoding an address signal to select a normal signal line, a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line, and a test control circuit for controlling the decoder and the spare decoder to perform a test of applying voltage between adjacent signal lines in the normal signal lines and the spare signal lines.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Abstract: In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.