Abstract: In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

Abstract: A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit.

Abstract: A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.

Abstract: A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node, and a plurality of MOS transistors which are connected in cascade, a plurality of data storage capacitors, formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.

Abstract: A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

Abstract: A DRAM comprising a memory cell array having a dynamic type memory cell having one MOS transistor for transfer gate and one capacitor for data storage with one end connected to the transistor, a word line connected in common to the gate of each transistor in each row of the memory cell array, a bit line connected in common to each transistor in each column of the memory cell array, a bit line precharge circuit provided so as to precharge the bit line of the memory cell array at a predetermined timing, a capacitor common line provided so as to correspond to a pair of complementary bit lines of the memory cell array and connected in common to the other end of the capacitor of the memory cell, a capacitor common precharge circuit provided so as to precharge the capacitor common line at predetermined timing, capacitor common line transfer gates for connecting the capacitor common line to the input nodes of a sense amplifier and on/off controlled at a predetermined timing, and bit line transfer gates for connectin

Abstract: A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.