Patents by Inventor Satoshi Eguchi

Satoshi Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10495031
    Abstract: A heater for a canister includes a heater case embedded within an adsorption material and sealed at a top, and a heater core having a heat generation element and installed in the heater case. The bottom of the heater case is fitted into a heater retaining hole of a cap member in a hermetically-sealed state, for enabling the heat generation element and terminals of the heater core to be completely separated from the gas atmosphere containing the adsorbed fuel components within an activated carbon region. A leaf spring having a heat conductivity is arranged between an outside surface of one of a pair of strip-shaped ceramic plates constructing part of the heater core and an inner wall surface of the heater case, for retaining the heater core in place within the heater case and for permitting heat transfer from the heat generation element to the adsorption material.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 3, 2019
    Assignee: MAHLE FILTER SYSTEMS JAPAN CORPORATION
    Inventors: Junpei Omichi, Shuichi Eguchi, Satoshi Seki
  • Patent number: 10466629
    Abstract: In a fixing device of the present invention, first and second movable members are each urged toward a flexible member so that the contact between contact surfaces of the first and second movable members and end faces of the flexible member are each maintained.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: November 5, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Murasaki, Motoyasu Muramatsu, Hiroki Eguchi
  • Patent number: 10386252
    Abstract: A position control apparatus is provided that can perform accurate nonlinear compensation control immediately after the apparatus is activated. At a time of acceleration, a signal amplification ratio is calculated and designated for each signal vector element based on information related to acceleration/deceleration at a starting time and the structure of a signal vector that is determined for a target plant, and as a result, a signal vector for which the strength of linear independence is increased is generated. Because the strength of the linear independence condition of the signal vector is increased, the speed of convergence of identification for a low-frequency disturbance element, such as a gravitational torque or a sliding-mode load torque, can be increased.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 20, 2019
    Assignee: OKUMA CORPORATION
    Inventor: Satoshi Eguchi
  • Publication number: 20190237577
    Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
  • Publication number: 20190238079
    Abstract: A controller for a motor determines a voltage limit circle based on a velocity of the motor, a DC bus voltage of an inverter, calculates a q axis current limit value based on the voltage limit circle and a predetermined current limit circle, determines, as a q axis current command value, a value obtained through a limit process which is applied using the q axis current limit value to a q axis current value calculated in accordance with a torque command value, and determines a corresponding d axis current value based on the q axis current command value.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 1, 2019
    Inventor: Satoshi EGUCHI
  • Patent number: 10361258
    Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element faulted over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura, Satoshi Seo, Kaoru Hatano
  • Patent number: 10355122
    Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Shigeaki Saito, Daisuke Taniguchi, Natsuo Yamaguchi
  • Publication number: 20190207001
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Yuya ABIKO, Natsuo YAMAGUCHI, Satoshi EGUCHI
  • Publication number: 20190198663
    Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.
    Type: Application
    Filed: November 15, 2018
    Publication date: June 27, 2019
    Inventors: Atsushi SAKAI, Katsumi EIKYU, Satoshi EGUCHI, Nobuo MACHIDA, Koichi ARAI, Yasuhiro OKAMOTO, Kenichi HISADA, Yasunori YAMASHITA
  • Publication number: 20190189856
    Abstract: An object is to provide a highly reliable light emitting device which is thin and is not damaged by external local pressure. Further, another object is to manufacture a light emitting device with a high yield by preventing defects of a shape and characteristics due to external stress in a manufacture process. A light emitting element is sealed between a first structure body in which a fibrous body is impregnated with an organic resin and a second structure body in which a fibrous body is impregnated with an organic resin, whereby a highly reliable light emitting device which is thin and has intensity can be provided. Further, a light emitting device can be manufactured with a high yield by preventing defects of a shape and characteristics in a manufacture process.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 20, 2019
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki OIKAWA, Shingo Eguchi, Mitsuo Mashiyama, Masatoshi Kataniwa, Hironobu Shoji, Masataka Nakada, Satoshi Seo
  • Patent number: 10204987
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida
  • Patent number: 10141397
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Publication number: 20180286952
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Application
    Filed: February 5, 2018
    Publication date: October 4, 2018
    Inventors: Yuya ABIKO, Natsuo YAMAGUCHI, Satoshi EGUCHI
  • Patent number: 10073436
    Abstract: A fully-closed loop position controller with a velocity control system based on a velocity feedback of mixed velocities of a motor velocity and a load velocity. The fully-closed loop position controller identifies a ratio of load moment of inertia in real time to select an optimum mix gain in accordance with a changing ratio of load moment of inertia such that a position loop gain and a speed loop gain can be varied accordingly. The fully-closed loop position controller controls the load position based on the mix gain, the position loop gain, and the velocity loop gain.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 11, 2018
    Assignee: OKUMA CORPORATION
    Inventor: Satoshi Eguchi
  • Publication number: 20180240905
    Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 23, 2018
    Inventors: Satoshi EGUCHI, Tetsuya IIDA, Akio ICHIMURA, Yuya ABIKO
  • Patent number: 9997621
    Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 12, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Hitoshi Matsuura, Yuya Abiko
  • Publication number: 20180158910
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Inventors: Yuya ABIKO, Satoshi EGUCHI, Akio ICHIMURA, Natsuo YAMAGUCHI, Tetsuya IIDA
  • Patent number: 9972713
    Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 15, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Eguchi, Tetsuya Iida, Akio Ichimura, Yuya Abiko
  • Publication number: 20180076313
    Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).
    Type: Application
    Filed: June 30, 2017
    Publication date: March 15, 2018
    Inventors: Yuya ABIKO, Satoshi EGUCHI, Shigeaki SAITO, Daisuke TANIGUCHI, Natsuo YAMAGUCHI
  • Patent number: 9905644
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida