Patents by Inventor Satoshi Eguchi

Satoshi Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140299961
    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA, Satoshi EGUCHI
  • Publication number: 20140284705
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Application
    Filed: June 10, 2014
    Publication date: September 25, 2014
    Inventors: Satoshi EGUCHI, Yuya ABIKO, Junichi KOGURE
  • Patent number: 8796094
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure
  • Publication number: 20140206162
    Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 24, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Satoshi EGUCHI, Daisuke TANIGUCHI
  • Patent number: 8786046
    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa, Satoshi Eguchi
  • Publication number: 20140191309
    Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi EGUCHI, Yoshito NAKAZAWA, Tomohiro TAMAKI
  • Publication number: 20140120669
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 1, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi EGUCHI, Yuya ABIKO, Junichi KOGURE
  • Patent number: 8647948
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: February 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure
  • Patent number: 8563393
    Abstract: A method for manufacturing a semiconductor device which prevents damage to alignment marks used for alignment between a superjunction structure and process layers at subsequent steps. In the related art, recesses are made in a semiconductor substrate before the formation of the superjunction structure and used as alignment marks and in order to prevent damage to the alignment marks, the alignment marks are covered by an insulating film such as a silicon oxide film during the subsequent process of forming the superjunction structure, but the inventors have found that damage may penetrate the cover film, reach the semiconductor substrate and destroy the marks. In the method according to the invention, alignment marks for alignment between the superjunction structure and process layers at subsequent steps are formed after the formation of the superjunction structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: October 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Hitoshi Seshimo, Naoko Shimizu
  • Publication number: 20130264650
    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA, Satoshi EGUCHI
  • Patent number: 8390615
    Abstract: A television 1 of the present invention is a television 1 for processing display data and displaying an image based on the processed display data, the display data containing the image and a control script that defines at least a function of displaying the image, wherein the television 1 includes a basic function executing section 42 for executing a basic function program called from the control script, the basic function program being stored in a basic function program storage section 29; and a control script executing section 41 for controlling basic function executing section 42 according to the control script so as to perform a first function for displaying the image, the first function being defined by the control script, the control script further defines a second function which the television 1 performs while the image is being displayed by the first function, and the control script executing section 41 controls the basic function executing section 42 according to the control script so as to execute th
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: March 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirofumi Furukawa, Masafumi Hirata, Soichi Nitta, Tatsuo Sudo, Azusa Umemoto, Aya Enatsu, Masafumi Takahashi, Takuya Kinoshita, Kiyotaka Kashito, Katsuo Doi, Satoshi Eguchi, Hideyuki Otokawa, Kentaro Sakakura, Masaki Hasiura
  • Publication number: 20120006798
    Abstract: A laser oscillator includes a blower for blowing laser gas to discharge tubes; a gas circulation path for connecting discharge tubes and a blower; a gear chamber pressure detector for detecting the pressure of the gear chamber disposed in the blower; and an alarm part for issuing an alarm when the pressure detected in the gear chamber pressure detector is higher than a predetermined pressure. The predetermined pressure is set based on the average value of the pressure on the laser gas inlet side and the pressure on the laser gas outlet side of the blower. This configuration can prevent the entry of the oil mist generated from the blower into the gas circulation path and an increase in the gas consumption, while maintaining stable laser output for an extended period of time without increasing the running cost.
    Type: Application
    Filed: March 8, 2010
    Publication date: January 12, 2012
    Applicant: Panasonic Corporation
    Inventors: Satoshi Eguchi, Hidefumi Omatsu, Hiroyuki Hayashikawa
  • Patent number: 8082048
    Abstract: A structure is provided in which a thrust feed forward structure for operating a structure to be driven without vibration and a control structure which simultaneously compensates for positional deviation caused by the thrust feed forward structure and positional deviation caused by a base displacement are included in a position controlling device (3). Alternatively, a structure is provided in which an acceleration and deceleration process for realizing response of the position of the structure to be driven and base displacement without vibration and a control structure which determines a feed forward amount with respect to a position instruction value after the acceleration and deceleration process are provided to the position controlling device.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 20, 2011
    Assignee: Okuma Corporation
    Inventor: Satoshi Eguchi
  • Publication number: 20110294278
    Abstract: A method for manufacturing a semiconductor device which prevents damage to alignment marks used for alignment between a superjunction structure and process layers at subsequent steps. In the related art, recesses are made in a semiconductor substrate before the formation of the superjunction structure and used as alignment marks and in order to prevent damage to the alignment marks, the alignment marks are covered by an insulating film such as a silicon oxide film during the subsequent process of forming the superjunction structure, but the inventors have found that damage may penetrate the cover film, reach the semiconductor substrate and destroy the marks. In the method according to the invention, alignment marks for alignment between the superjunction structure and process layers at subsequent steps are formed after the formation of the superjunction structure.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Satoshi EGUCHI, Hitoshi Seshimo, Naoko Shimizu
  • Publication number: 20110284957
    Abstract: To fabricate a power MOSFET, etc. high in voltage-proofing (or breakdown voltage) and low in ON resistance (or On-state resistance) by a trench filling method, trial manufacture of power MOSFETs, etc. has been repeated with varying internal structures and layouts of super junction structures in a chip inner region located inside a guard ring. As a result, there occasionally occurred a source-drain voltage-proofing defect attributable to outer end portions of a supper junction structure. In one aspect of the present invention there is provided a semiconductor device having a power semiconductor element with a super junction structure introduced substantially throughout the whole surface of a drift region, the super junction structure being provided substantially throughout the whole surfaces of end portions of a semiconductor chip which configures the semiconductor device.
    Type: Application
    Filed: April 25, 2011
    Publication date: November 24, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA, Satoshi EGUCHI
  • Publication number: 20110115033
    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa, Satoshi Eguchi
  • Patent number: 7750592
    Abstract: When performing numerical control of a rotary table, the moment of inertia and the center of gravity of a control target change because of a placed object fixed onto the rotary table. A rotary table to which a placed object has been fixed serves as a target plant, the actual motion of this is compared with motion calculated by an identification model of the target plant, and a torque command value is corrected. The identification model comprises a term pertaining to angular acceleration and a term pertaining to angle of rotation, and by including the term pertaining to angle of rotation, correction of a torque command corresponding to a change in the center of gravity can be performed.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: July 6, 2010
    Assignee: Okuma Corporation
    Inventor: Satoshi Eguchi
  • Patent number: 7655528
    Abstract: SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at predetermined flow rates, and SiGe:C is formed by an epitaxial growth technique. By diluting the SiH3CH3, the concentration of oxygen-based impurity contained in the SiH3CH3 is reduced and hence, the oxygen-based impurity which is supplied to a chamber are reduced whereby the concentration of oxygen-based impurity contained in the SiGe:C formed in a film is reduced.
    Type: Grant
    Filed: January 17, 2005
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Eguchi, Akira Kanai, Isao Miyashita, Seigo Nagashima
  • Publication number: 20090112376
    Abstract: A structure is provided in which a thrust feed forward structure for operating a structure to be driven without vibration and a control structure which simultaneously compensates for positional deviation caused by the thrust feed forward structure and positional deviation caused by a base displacement are included in a position controlling device (3). Alternatively, a structure is provided in which an acceleration and deceleration process for realizing response of the position of the structure to be driven and base displacement without vibration and a control structure which determines a feed forward amount with respect to a position instruction value after the acceleration and deceleration process are provided to the position controlling device.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 30, 2009
    Applicant: OKUMA CORPORATION
    Inventor: Satoshi Eguchi
  • Publication number: 20080169778
    Abstract: When performing numerical control of a rotary table, the moment of inertia and the center of gravity of a control target change because of a placed object fixed onto the rotary table. A rotary table to which a placed object has been fixed serves as a target plant, the actual motion of this is compared with motion calculated by an identification model of the target plant, and a torque command value is corrected. The identification model comprises a term pertaining to angular acceleration and a term pertaining to angle of rotation, and by including the term pertaining to angle of rotation, correction of a torque command corresponding to a change in the center of gravity can be performed.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 17, 2008
    Applicant: Okuma Corporation
    Inventor: Satoshi Eguchi