Patents by Inventor Satoshi Horiuchi
Satoshi Horiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12334033Abstract: Provided is a display device including gate drive circuits, a signal line connected to the gate drive circuit, a signal line connected to the gate drive circuit, a gate terminal, inspection terminals, and a connection line. The connection line connects the signal line and the signal line. The inspection terminal is disposed on the signal line. The inspection terminal is disposed on the signal line. The inspection terminals are terminals input with an inspection signal at the time of inspection.Type: GrantFiled: August 22, 2023Date of Patent: June 17, 2025Assignee: Sharp Display Technology CorporationInventors: Satoshi Horiuchi, Akane Sugisaka, Seiya Kawamorita, Shinji Matsubara
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Publication number: 20250123716Abstract: A drive circuit includes a plurality of stages and configured to supply a drive signal to a scanning signal line group in response to input of a plurality of clock signals. The drive circuit includes a plurality of unit circuits respectively constituting the plurality of stages, the plurality of unit circuits being configured to output the drive signal, a latch circuit provided in parallel with the plurality of unit circuits, and a connection circuit connected to an output node of the latch circuit.Type: ApplicationFiled: September 23, 2024Publication date: April 17, 2025Inventors: Yasuaki IWASE, Seijirou GYOUTEN, Satoshi HORIUCHI, Shinji MATSUBARA
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Publication number: 20250123715Abstract: A drive circuit comprising a plurality of stages comprises a latch circuit configured to retain an output signal inputted from a preceding stage in a suspension period in which the drive circuit is suspended and configured to supply the output signal to a succeeding stage when the suspension period ends, the latch circuit includes a signal retaining node; a first transistor including a first electrode supplied a first control signal when the suspension period ends and a first control electrode; a second output node connected to the first control electrode; and a second transistor including a second control electrode supplied a second control signal supplied after the suspension period starts, but before the first control signal is supplied to the first electrode, the second transistor electrically connects the signal retaining node and the second output node by the second control signal supplied to the second control electrode.Type: ApplicationFiled: September 18, 2024Publication date: April 17, 2025Inventors: Seiya KAWAMORITA, Satoshi HORIUCHI, Yasuaki IWASE, Shinji MATSUBARA
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Patent number: 12243878Abstract: An active matrix substrate includes a substrate in which a notch or an aperture is formed, and electrodes. Each electrode includes at least either of: a capacitor forming portion that is arranged in a region other than a bypass region and overlaps with at least one of a plurality of bypass gate lines when viewed in a plan view; and an electrode layer portion that is formed in an electrode layer and that composes a bypass gate line interposed portion together with a source line layer portion formed in a source line layer in the bypass region. The electrode layer portion and the source line layer portion overlap with at least one of the bypass gate lines in the bypass region when viewed in a plan view, and at least one of the bypass gate lines is positioned between the electrode layer portion and the source line layer portion in a normal line direction of the substrate.Type: GrantFiled: October 11, 2022Date of Patent: March 4, 2025Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Hikaru Yoshino, Satoshi Horiuchi, Junichi Morinaga
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Patent number: 12100358Abstract: A unit circuit constituting each of stages of a shift register is provided with a thin film transistor, the thin film transistor including a control terminal applied with one of a plurality of gate clock signals, a first conduction terminal connected to a third node, and a second conduction terminal applied with a direct current power supply voltage of a low level. The third node is connected to a control terminal of a thin film transistor configured to change a potential of a second node toward a high level. When a gate clock signal applied to a control terminal of a thin film transistor configured to change a potential of the third node toward the high level changes from the high level to the low level, the gate clock signal applied to the control terminal of the thin film transistor changes from the low level to the high level.Type: GrantFiled: November 8, 2023Date of Patent: September 24, 2024Assignee: Sharp Display Technology CorporationInventors: Seiya Kawamorita, Satoshi Horiuchi, Yasuaki Iwase
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Publication number: 20240194151Abstract: A unit circuit constituting each of stages of a shift register is provided with a thin film transistor, the thin film transistor including a control terminal applied with one of a plurality of gate clock signals, a first conduction terminal connected to a third node, and a second conduction terminal applied with a direct current power supply voltage of a low level. The third node is connected to a control terminal of a thin film transistor configured to change a potential of a second node toward a high level. When a gate clock signal applied to a control terminal of a thin film transistor configured to change a potential of the third node toward the high level changes from the high level to the low level, the gate clock signal applied to the control terminal of the thin film transistor changes from the low level to the high level.Type: ApplicationFiled: November 8, 2023Publication date: June 13, 2024Inventors: Seiya KAWAMORITA, Satoshi HORIUCHI, Yasuaki IWASE
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Publication number: 20240105139Abstract: Provided is a display device including gate drive circuits, a signal line connected to the gate drive circuit, a signal line connected to the gate drive circuit, a gate terminal, inspection terminals, and a connection line. The connection line connects the signal line and the signal line. The inspection terminal is disposed on the signal line. The inspection terminal is disposed on the signal line. The inspection terminals are terminals input with an inspection signal at the time of inspection.Type: ApplicationFiled: August 22, 2023Publication date: March 28, 2024Inventors: Satoshi HORIUCHI, Akane SUGISAKA, Seiya KAWAMORITA, Shinji MATSUBARA
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Publication number: 20230112631Abstract: An active matrix substrate includes a substrate in which a notch or an aperture is formed, and electrodes. Each electrode includes at least either of: a capacitor forming portion that is arranged in a region other than a bypass region and overlaps with at least one of a plurality of bypass gate lines when viewed in a plan view; and an electrode layer portion that is formed in an electrode layer and that composes a bypass gate line interposed portion together with a source line layer portion formed in a source line layer in the bypass region. The electrode layer portion and the source line layer portion overlap with at least one of the bypass gate lines in the bypass region when viewed in a plan view, and at least one of the bypass gate lines is positioned between the electrode layer portion and the source line layer portion in a normal line direction of the substrate.Type: ApplicationFiled: October 11, 2022Publication date: April 13, 2023Inventors: Hikaru YOSHINO, Satoshi HORIUCHI, Junichi MORINAGA
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Patent number: 11552109Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.Type: GrantFiled: January 19, 2021Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihiro Asai, Satoshi Horiuchi, Seiya Kawamorita, Shinji Matsubara, Seijirou Gyouten
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Patent number: 11374037Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).Type: GrantFiled: February 14, 2018Date of Patent: June 28, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Satoshi Horiuchi, Yoshihiro Asai, Isao Ogasawara, Masakatsu Tominaga, Yoshihito Hara
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Patent number: 11333939Abstract: A display device includes a conventional first auxiliary trunk line formed to be narrow, and a second auxiliary trunk line additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole.Type: GrantFiled: December 16, 2020Date of Patent: May 17, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
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Patent number: 11200862Abstract: A unit circuit of a shift register includes an output transistor whose control terminal is connected to a first node, first and second set transistors, first and second reset transistors, a control signal generating circuit that generates a control signal that changes to an on level when a first clock signal changes to an on level while the potential of the first node is at an off level, and that outputs the generated control signal to the unit circuits at a preceding stage and a next stage, a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the preceding stage, and a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the next stage.Type: GrantFiled: April 8, 2021Date of Patent: December 14, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Seijirou Gyouten, Satoshi Horiuchi
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Publication number: 20210335311Abstract: A unit circuit of a shift register includes an output transistor whose control terminal is connected to a first node, first and second set transistors, first and second reset transistors, a control signal generating circuit that generates a control signal that changes to an on level when a first clock signal changes to an on level while the potential of the first node is at an off level, and that outputs the generated control signal to the unit circuits at a preceding stage and a next stage, a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the preceding stage, and a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the next stage.Type: ApplicationFiled: April 8, 2021Publication date: October 28, 2021Inventors: Seijirou Gyouten, Satoshi Horiuchi
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Patent number: 11150706Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.Type: GrantFiled: May 28, 2020Date of Patent: October 19, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Satoshi Horiuchi, Seijirou Gyouten, Yoshihiro Asai, Seiya Kawamorita
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Publication number: 20210225879Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.Type: ApplicationFiled: January 19, 2021Publication date: July 22, 2021Inventors: Yoshihiro ASAI, Satoshi HORIUCHI, Seiya KAWAMORITA, Shinji MATSUBARA, Seijirou GYOUTEN
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Publication number: 20210103176Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Masahiro YOSHIDA, Isao OGASAWARA, Satoshi HORIUCHI, Takaharu YAMADA
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Patent number: 10957268Abstract: An active-matrix substrate according to an embodiment of the present invention includes a plurality of first TFTs that are arranged within a display area, an inorganic insulating layer that covers the plurality of first TFTs, an organic insulating layer that is provided on the inorganic insulating layer, a plurality of second TFTs that are arranged within a non-display area, and a source and gate metal connection portion that is positioned within the non-display area, a first conductive layer that is formed from an identical conductive film with a gate wiring line and a second conductive layer that is formed from an identical conductive film with a source wiring line being connected to each other at the source and gate metal connection portion. Each of the plurality of first TFTs is an oxide semiconductor TFT. At least one second TFT among the plurality of second TFTs is covered with the organic insulating layer. The source and gate metal connection portion is not covered with the organic insulating layer.Type: GrantFiled: August 4, 2017Date of Patent: March 23, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hajime Imai, Takashi Terauchi, Shinya Ohira, Isao Ogasawara, Satoshi Horiuchi
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Patent number: 10877333Abstract: A display device includes a conventional first auxiliary trunk line formed to be narrow, and a second auxiliary trunk line additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole.Type: GrantFiled: October 1, 2018Date of Patent: December 29, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
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Publication number: 20200379523Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.Type: ApplicationFiled: May 28, 2020Publication date: December 3, 2020Inventors: Satoshi HORIUCHI, Seijirou GYOUTEN, Yoshihiro ASAI, Seiya KAWAMORITA
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Publication number: 20200346450Abstract: A decorative laminate of the present invention includes a transparent film, a coating layer constituted of a hard resin material and disposed on a side of a first surface which is one surface of the transparent film, a shielding layer disposed on a side of a second surface of the transparent film, which is the other surface opposite to the first surface, and a printed layer disposed between the coating layer and the shielding layer.Type: ApplicationFiled: January 22, 2019Publication date: November 5, 2020Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Kosaku TAMURA, Satoshi HORIUCHI, Toshinori KIFUKU