Patents by Inventor Satoshi Horiuchi

Satoshi Horiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160053992
    Abstract: Problem to be Solved To provide a waste gasification melting apparatus which, even if a fuel gas is used as an alternative to a part of the coke, the temperature of the coke bed can be sufficiently raised, and a method using the same. Solution A waste gasification melting apparatus including an oxygen rich air supply apparatus 14 for blowing oxygen rich air into a tuyere 5, and a fuel gas supply apparatus 15 for supplying a fuel gas to the tuyere 5, and a controller 16 for controlling the oxygen rich air supply apparatus 14; the oxygen rich air supply apparatus 14 mixing air and oxygen to prepare oxygen rich air and supply the oxygen rich air to the tuyere 5; and the controller 16 controlling the amount of air to be mixed and the amount of oxygen to be mixed in the oxygen rich air supply apparatus 14 so as to give an oxygen concentration of the oxygen rich air in accordance with the amount of fuel gas supplied to the tuyere 5 from the fuel gas supply apparatus 15.
    Type: Application
    Filed: March 27, 2014
    Publication date: February 25, 2016
    Applicant: JFE Engineering Corporation
    Inventors: Satoshi Horiuchi, Keiichi Okuyama, Takeshi Uchiyama, Hajime Akiyama, Junya Watanabe, Takashi Nakayama, Kazumasa Wakimoto, Akio Shimomura
  • Patent number: 9261741
    Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: February 16, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
  • Patent number: 9223161
    Abstract: The present invention provides a display device in which a seal is easily inspected.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 29, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isao Ogasawara, Masahiro Yoshida, Satoshi Horiuchi
  • Patent number: 9208741
    Abstract: On a display panel 10, a first scanning signal line drive circuit 12 is formed along a side of a display region 11 and a second scanning signal line drive circuit 13 is formed along the opposite side by the same process as pixel circuits. The size of a transistor included, the width of a wiring line, or the like, differs between the first and second scanning signal line drive circuits 12 and 13, and the two scanning signal line drive circuits have different sizes in a lateral direction. By this, the center of the display region matches that of a non-integral-type display panel, ensuring compatibility with the non-integral-type display panel. Moreover, by suitably determining the widths of or spacings between wiring lines included in the two scanning signal line drive circuits, leakage between the wiring lines and breaks in the wiring lines are reduced, improving yield of display panels.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 8, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuyoshi Ueda, Isao Ogasawara, Satoshi Horiuchi, Shinya Tanaka, Tetsuo Kikuchi, Masahiro Yoshida
  • Patent number: 9070812
    Abstract: An active matrix substrate includes: an electrode layer formed on the insulating substrate within a display region; a mark disposed on the insulating substrate within a non-display region, and made of a same material as the electrode layer; a first insulating film directly covering each of the electrode layer and the mark; and a second insulating film covering a part of the first insulating film. Within at least a part of the sealing region, the second insulating film is removed from the insulating substrate. The mark is disposed in the at least the part of the sealing region in which the second insulating film is removed, and is provided to overlap at least a part of the sealing region. A protective film is formed on the insulating substrate to cover a side surface and a surface of the first insulating film covering the mark, the surface of the first insulating film being located opposite from the insulating substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 30, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Yoshida, Takaharu Yamada, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Patent number: 9036121
    Abstract: Picture element electrodes (7) are electrically connected with drain electrodes (18D) of respective transistor elements (18). The picture element electrodes (7) and data signal lines (SLn, SLn+1, . . . ) are provided above scanning signal lines (GLn, GLn+1, . . . ). The picture element electrodes (7) overlap scanning signal lines (GLn, GLn+1, . . . ) when viewed from above. Notch parts 7a and 7b are provided in each picture element electrode (7) so as to overlap each of the scanning signal lines (GLn, GLn+1, . . . ). Shield electrodes (4a, 4b) are formed in the same layer as the data signal lines (SLn, SLn+1, . . . ). Each of the scanning signal lines (GLn, GLn+1, . . . ) at least partially overlaps the shield electrodes (4a, 4b) in the notch parts (7a, 7b), when viewed from above. This provides the liquid crystal display panel having wide viewing angle characteristic and carrying out high quality display.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 19, 2015
    Assignee: UNIFIED INNOVATIVE TECHNOLOGY, LLC
    Inventors: Ryohki Itoh, Yuhko Hisada, Satoshi Horiuchi, Takaharu Yamada, Masahiro Yoshida
  • Publication number: 20150070616
    Abstract: The present invention provides a display device in which a seal is easily inspected.
    Type: Application
    Filed: February 6, 2013
    Publication date: March 12, 2015
    Inventors: Isao Ogasawara, Masahiro Yoshida, Satoshi Horiuchi
  • Patent number: 8975638
    Abstract: The active matrix substrate is provided with: first and second scan lines (20a, 20b) that extend in a first direction; first and second signal lines (30a, 30b) that extend in a second direction; first and second pixels (10a, 10b) that are arranged adjacent to each other along the second direction; an auxiliary capacitor line (40); first and second pixel electrodes (60a, 60b); a first TFT (50a); a second TFT (50b); an auxiliary capacitor electrode (42) that is connected to the auxiliary capacitor line (40) and extends below the first and second pixel electrodes (60a, 60b); a first auxiliary capacitor counter electrode (62a) that is connected to the first pixel electrode (60a); and a second auxiliary capacitor counter electrode (62b) that is connected to the second pixel electrode (60b).
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyori Mitsumoto, Masahiro Yoshida, Satoshi Horiuchi
  • Publication number: 20150030116
    Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int
    Type: Application
    Filed: March 5, 2013
    Publication date: January 29, 2015
    Inventors: Satoshi Horiuchi, Shinya Tanaka, Akira Tagawa, Yasuaki Iwase, Takayuki Mizunaga, Akihisa Iwamoto
  • Patent number: 8941185
    Abstract: An active matrix substrate of the present invention includes: a first signal line and a second signal line which are aligned in a column direction in which the first signal line and the second signal line extend; a first transistor and a second transistor; and a first electrode and a second electrode, the first signal line being connected via the first transistor to the first electrode, and the second signal line being connected via the second transistor to the second electrode, and the first signal line having a first end which is one of both ends of the first signal line and faces the second signal line, the first end including a tapered part which is tapered toward the second signal line. This makes it possible to prevent a leakage defect from occurring between two signal lines which are aligned in a direction in which the two signal lines extend.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Publication number: 20140306948
    Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.
    Type: Application
    Filed: August 9, 2012
    Publication date: October 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihisa Iwamoto, Hideki Morii, Takayuki Mizunaga, Kazuya Nakaminami, Satoshi Horiuchi
  • Publication number: 20140267969
    Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Isao OGASAWARA, Takaharu YAMADA, Masahiro YOSHIDA, Satoshi HORIUCHI, Shinya TANAKA, Tetsuo KIKUCHI
  • Patent number: 8780311
    Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isao Ogasawara, Takaharu Yamada, Masahiro Yoshida, Satoshi Horiuchi, Shinya Tanaka, Tetsuo Kikuchi
  • Publication number: 20140191935
    Abstract: The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).
    Type: Application
    Filed: August 3, 2012
    Publication date: July 10, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Morii, Akihisa Iwamoto, Satoshi Horiuchi, Takayuki Mizunaga, Kazuya Nakaminami
  • Patent number: 8743240
    Abstract: Disclosed is an imaging apparatus with a flicker detector that restrains an increased calculation amount and image quality degradation. The apparatus includes a frame rate controller for setting a frame rate of an acquired image to a first frame rate or different second frame rate, a luminance calculator for calculating a first luminance difference between two images of a first group continuously acquired at the first frame rate and a second luminance difference between two images of a second group continuously acquired at the second frame rate, and a flicker detector for comparing the first and second luminance differences with first and second threshold, respectively, and determining whether flickers of a first frequency and a different second frequency are generated or not.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Satoshi Horiuchi
  • Patent number: 8743305
    Abstract: A liquid crystal display device in which lengths (d1 and1 d2) of respective picture element electrodes (60) in an extended direction of scanning signal lines (32) are longer than lengths (d3) of the respective picture element electrodes (60) in an extended direction of video signal lines (35) is arranged such that storage capacitor lines (36) are provided along the respective scanning signal lines (32) so as to overlap the respective picture element electrodes (60) via an insulating film (70) in plan view.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: June 3, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Yoshida, Satoshi Horiuchi, Masakatsu Tominaga, Junichi Morinaga, Ryohki Itoh, Katsushige Asada, Hironobu Sawada, Hitoshi Matsumoto
  • Patent number: 8735887
    Abstract: The present invention provides an ion sensor with which an ion concentration can be stably measured with high accuracy, and a display device. The present invention is an ion sensor that includes a field effect transistor. The ion sensor also includes an ion sensor antenna and a reset device. The ion sensor antenna and the reset device are connected to a gate electrode of the field effect transistor. The reset device is capable of controlling the potential of the gate electrode and the ion sensor antenna to a predetermined potential.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: May 27, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsuhito Murai, Yoshiharu Kataoka, Takuya Watanabe, Yuhko Hisada, Satoshi Horiuchi
  • Patent number: 8736779
    Abstract: A high-quality display is achieved by suppressing a disturbance in alignment in a liquid crystal display panel including a substrate structured so that a slit in a pixel electrode intersects with a scanning signal line or an auxiliary capacitor line. An active matrix substrate (10) includes: a pixel electrode (12) having a slit; and an auxiliary capacitor line (14). In a region of intersection between the slit (15) and the auxiliary capacitor line (14) or a scanning signal line (21), at least a drain line (13) or a data signal line (22) is provided between a layer of the pixel electrode (12) and a layer of the auxiliary capacitor line (14) or of the scanning signal line (21) in such a way as to cover the auxiliary capacitor line (12) or the scanning signal line (21).
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: May 27, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Horiuchi, Takaharu Yamada, Yuhko Hisada, Ryohki Itoh
  • Patent number: 8723845
    Abstract: A signal distribution circuit (3) includes (i) a redundancy TFT element (8) provided so as to have a channel width identical to those of driving TFT elements (7), (ii) first redundancy lines (9a, 9b), (iii) a second redundancy line (10), and (iv) a third redundancy line (11). It is therefore possible to provide a liquid crystal display device including the signal distribution circuit (3) in which, even in a case where a leaking part (a defect part) is generated in any of the driving TFT elements (7), it does not take long to restore the leaking part, and productivity can be improved, the driving TFT elements (7) keeping respective channel widths identical to one another even after the leaking part is restored.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: May 13, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada, Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi
  • Patent number: 8717268
    Abstract: A display device prevents luminance unevenness that occurs in the case of inversion driving being performed, and performs high quality image display, while selectively scanning two lines of picture elements constituting a single pixel using a single gate wiring, as in the case of multi-primary color image display.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: May 6, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ryohki Itoh, Satoshi Horiuchi, Yuhko Hisada