Abstract: A method for producing a printed material includes providing pressure-induced phase transition particles on a recording medium having an arithmetic average roughness Ra of 0.07 ?m or more and 3.80 ?m or less to form a pressure-induced phase transition particle layer having a coverage C within a range of 30% to 90%; bonding the pressure-induced phase transition particles onto the recording medium; and folding the recording medium having the pressure-induced phase transition particles bonded thereon and pressure-bonding the folded recording medium, or pressure-bonding the recording medium having the pressure-induced phase transition particles bonded thereon and another recording medium placed on top of each other.

Abstract: A honeycomb-structured catalyst for decomposing an organic substance, which includes a catalyst particle. The catalyst particle contains a perovskite-type composite oxide represented by AxByMzOw, where the A contains at least of Ba and Sr, the B contains Zr, the M is at least one of Mn, Co, Ni, and Fe, y+z=1, 1.001?x?1.05, 0.05?z?0.2, and w is a positive value that satisfies electrical neutrality. The toluene decomposition rate is greater than 90% when toluene is decomposed using the honeycomb-structured catalyst subjected to a heat treatment at 1200° C. for 48 hours and a gas that contains 50 ppm toluene, 80% nitrogen, and 20% oxygen as a volume concentration as a target at a space velocity of 30,000/h and a catalyst temperature of 400° C.

Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.

Abstract: An organic matter decomposition catalyst that contains a perovskite type complex oxide represented by AxByMzOw, wherein A contains 90 at % or more of at least one element selected from the group consisting of Ba and Sr, B contains 80 at % or more of Zr, M is at least one element selected from the group consisting of Mn, Co, Ni, and Fe, y+z=1, x>1, z<0.4, and w is a positive value that satisfies electrical neutrality.

Abstract: A polyimide precursor solution contains a polyimide precursor, particles, and a water-based solvent that contains an amine compound (A), an organic solvent (B) other than the amine compound (A) and amide compounds, and water, in which a boiling point of the organic solvent (B) is higher than a boiling point of the amine compound (A), and is 200° C. or higher and 300° C. or lower.

Abstract: A catalyst for decomposing an organic substance, the catalyst having a body which has a plurality of pores and the body contains a perovskite-type composite oxide represented by AxByMzOw, where the A contains at least one selected from Ba and Sr, the B contains Zr, the M is at least one selected from Mn, Co, Ni, and Fe, 1.001?x?1.1, 0.05?z?0.2, y+z=1, and w is a positive value that satisfies electrical neutrality. The average pore diameter of the plurality of pores is 49 nm to 260 nm and the pore volume of each of the plurality of pores is 0.08 cm3/g to 0.37 cm3/g.

Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.

Abstract: A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

Abstract: A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

Abstract: A switch drive circuit includes a high-side power supply section, a latch circuit, a high-side driver, a low-side driver, and a high-side switch control circuit. The latch circuit latches a logical level of a high-side switching signal at the time of performing switching of a high-side switch. The high-side driver drives the high-side switch by the high-side switching signal outputted from the latch circuit. The low-side driver drives a low-side switch by a low-side switching signal. The high-side switch control circuit sets, at the time of stopping the switching of the high-side switch, a stop established state in which the logical level of the high-side switching signal is fixed at a stop logic level, and releases the stop established state at the time of performing the switching of the high-side switch.

Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.

Abstract: In order to transfer a signal for driving a high-side semiconductor power switch, a signal transfer device includes a transmitting circuit, a receiving circuit, and an insulating transformer provided between the transmitting circuit and the receiving circuit. In the insulating transformer, a secondary side of a set transformer part and a secondary side of a reset transformer part are magnetically coupled. The magnetic coupling direction is formed so that a secondary-side terminal of the transformer part and a secondary-side terminal of the transformer part can have polarities reverse to each other. Thus, it is possible to provide a signal transfer device for transferring a signal through an insulating transformer, in which occurrence of common-mode noise can be suppressed and a countermeasure circuit against the noise can be simplified.

Abstract: A switch drive circuit includes a high-side power supply section, a latch circuit, a high-side driver, a low-side driver, and a high-side switch control circuit. The latch circuit latches a logical level of a high-side switching signal at the time of performing switching of a high-side switch. The high-side driver drives the high-side switch by the high-side switching signal outputted from the latch circuit. The low-side driver drives a low-side switch by a low-side switching signal. The high-side switch control circuit sets, at the time of stopping the switching of the high-side switch, a stop established state in which the logical level of the high-side switching signal is fixed at a stop logic level, and releases the stop established state at the time of performing the switching of the high-side switch.

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract: In a startup circuit, an error amplifier receives a target voltage in a startup period that is a terminal voltage with a shape of a slope generated by charging a capacitor for soft starting with a current from a constant current circuit. A detecting circuit monitors variation of the terminal voltage and blocks pulse from a logic circuit until the terminal voltage, which has been zero volts at the moment of startup, reaches a predetermined threshold value. In this period, the detecting circuit disables the function of the error amplifier. It is not until the terminal voltage VCS reaches the predetermined threshold value and the PWM pulse begins to be delivered that the error amplifier is enabled. At this moment, startup control begins based on the difference between the terminal voltage and the feedback signal. Therefore, the output voltage never rises abruptly.

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

Abstract: A sensor signal output circuit includes: a buffer amplifier which amplifies an output of a temperature sensor; an operational amplifier which amplifies an output of the buffer amplifier; an oscillator which generates a triangular wave signal; and a comparator which compares the triangular wave signal with an output of the operational amplifier to generate a PWM signal. After an offset adjusting resistor of the operational amplifier is adjusted at first temperature, the amplitude of the triangular wave signal is set to adjust the pulse width of the PWM signal at the first temperature. After that, a gain adjusting resistor of the operational amplifier is set to adjust the pulse width of the PWM signal at a second temperature.

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.