Patents by Inventor Satoshi Sugahara
Satoshi Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8031041Abstract: An object of the invention is to provide a micro power converter of a step-up and step-down type without requiring more than two semiconductor switches, without increasing the size of a semiconductor chip, and without degrading efficiency. A micro power converter comprises a micro transformer composed of a planar transformer having a structure including a conductor wound on and through a planar magnetic core, and a semiconductor chip including semiconductor switches S1, S2, and a control circuit for controlling the switches. By constructing a flyback transformer using a micro transformer composed of a planar transformer, a micro power converter of a step-up and step-down type is provided having two semiconductor switches and an overall size comparable to a conventional micro power converter.Type: GrantFiled: December 1, 2008Date of Patent: October 4, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventor: Satoshi Sugahara
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Patent number: 8026563Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.Type: GrantFiled: September 22, 2010Date of Patent: September 27, 2011Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Patent number: 7960186Abstract: The disclosure provides a method of forming a ferromagnetic material, including: forming a magnetic element layer on a semiconductor layer formed on an inhibition layer; and forming a ferromagnetic layer of a Heusler alloy layer on the inhibition layer by heat treatment to induce the semiconductor layer and the magnetic element layer to react with each other, and a transistor, and a method of manufacturing the same. The inhibition layer for inhibiting a reaction of the semiconductor layer and the magnetic element layer restricts a semiconductor to be supplied for a reaction of the semiconductor and the magnetic element. Therefore, it is possible to form a ferromagnetic material having a high composition ratio of a magnetic element.Type: GrantFiled: March 26, 2008Date of Patent: June 14, 2011Assignee: Tokyo Institute of TechnologyInventors: Satoshi Sugahara, Yota Takamura
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Publication number: 20110080987Abstract: Among fuel rods constituting a fuel assembly, Gd compound oxide is added to low Gd containing fuel rods that containing uranium dioxide of which enrichment exceeds 5 wt %. The Gd compound oxide is oxide of gadolinium and rare earth element A except for gadolinium and is expressed as a chemical formula A1-xGdxO2-0.5x or a chemical formula A1-xGdxO1.5. As the rare earth element A, cerium Ce, lanthanum La or erbium Er can be used.Type: ApplicationFiled: October 14, 2010Publication date: April 7, 2011Inventors: Souichi WATANABE, Hironori Kumanomido, Ishi Mitsuhashi, Satoshi Sugahara, Makoto Ueda
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Patent number: 7906942Abstract: A DC-DC converter of a synchronous rectifier type, a control circuit thereof and control method thereof, facilitates detecting and interrupting negative inductor current IL with low power consumption, high accuracy and a simple configuration and facilitates improving the efficiency under a light load. An ON-period decision circuit determines whether an ON-period of the synchronous rectifier switch is too long or too short. An ON-period adjustment circuit generates a signal for adjusting the ON-period, during which the synchronous rectifier switch is ON, based on the decision of the ON-period decision part. A delay circuit adjusts the length of the delay, from the time when a signal changing the ON and OFF states of the synchronous rectifier switch changes to ON, to the time when the synchronous rectifier switch is forcibly turned off based on the adjusting signal.Type: GrantFiled: July 27, 2007Date of Patent: March 15, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventors: Satoshi Sugahara, Kouhei Yamada
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Publication number: 20110031545Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.Type: ApplicationFiled: September 22, 2010Publication date: February 10, 2011Applicant: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Patent number: 7851877Abstract: A logic circuit that can reconfigure its functions in a nonvolatile manner and a single-electron transistor to be used in the logic circuits are provided. The logic circuit has a single-electron spin transistor that includes: a source; a drain; an island that is provided between the source and the drain, and has tunnel junctions between the island and the source and drain; and a gate that is capacitively coupled to the island. In this logic circuit, at least one of the source, the drain, and the island includes a ferromagnetic material having a variable magnetization direction.Type: GrantFiled: February 2, 2006Date of Patent: December 14, 2010Assignee: Japan Science and Technology AgencyInventors: Masaaki Tanaka, Satoshi Sugahara, Hai Nam Pham
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Patent number: 7825485Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.Type: GrantFiled: October 31, 2007Date of Patent: November 2, 2010Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Patent number: 7812578Abstract: A DC-DC converter includes a series circuit of a main switch and a choke coil and an output capacitor connected to one end of the series circuit and outputs a DC voltage from the one end of the series circuit. A first MOS transistor is connected in parallel to the series circuit and a second MOS transistor is connected in parallel to the output capacitor. A control circuit controls the gate voltages of the first MOS transistor and/or the second MOS transistor so that the first MOS transistor and/or the second MOS transistor outputs a changed target output voltage, whereby the output voltage is made equal to the target voltage at high speed.Type: GrantFiled: June 3, 2008Date of Patent: October 12, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Satoshi Sugahara, Kouhei Yamada, Tetsuya Kawashima, Akira Yamazaki
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Patent number: 7764519Abstract: Control circuit and method for controlling a switching power supply, which regulates its output voltage using pulse-width modulation (PWM) that switches on and off a main switch with a PWM signal (VCONT) at an adjusted ON-period ratio of the main switch. The control circuit includes an error signal amplifier circuit that compares the output voltage with a reference voltage and outputs an error signal VE based on the comparison. The control circuit also includes an ON-period adjusting circuit that starts generating a PWM signal (VCONT) in every cycle based on a pulse VPULSE, the period thereof being fixed, and adjusts the HIGH-period of the PWM signal (VCONT) based on the output voltage of the error signal VE. As a result, the control circuit widens the HIGH-period ratio range or the LOW-period ratio range of the PWM signal greatly.Type: GrantFiled: May 22, 2008Date of Patent: July 27, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventor: Satoshi Sugahara
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Publication number: 20100171158Abstract: The present invention provides a method of forming a ferromagnetic material, characterized by including: forming a magnetic element layer 20 on a semiconductor layer 16 formed on an inhibition layer 14; and forming a ferromagnetic layer of a Heusler alloy layer 26 on the inhibition layer 14 by heat treatment to induce the semiconductor layer 16 and the magnetic element layer 20 to react with each other, and a transistor, and a method of manufacturing the same. According to the present invention, the inhibition layer for inhibiting a reaction of the semiconductor layer and the magnetic element layer restricts a semiconductor to be supplied for a reaction of the semiconductor and the magnetic element. Therefore, it is possible to form a ferromagnetic material having a high composition ratio of a magnetic element.Type: ApplicationFiled: March 26, 2008Publication date: July 8, 2010Applicant: TOKYO INSTITUTE OF TECHNOLOGYInventors: Satoshi Sugahara, Yota Takamura
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Patent number: 7714400Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.Type: GrantFiled: November 1, 2007Date of Patent: May 11, 2010Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Patent number: 7671433Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.Type: GrantFiled: October 31, 2007Date of Patent: March 2, 2010Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Publication number: 20090236646Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannon be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).Type: ApplicationFiled: March 17, 2009Publication date: September 24, 2009Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Satoshi Sugahara, Masaaki Tanaka
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Publication number: 20090146638Abstract: An object of the invention is to provide a micro power converter of a step-up and step-down type without requiring more than two semiconductor switches, without increasing the size of a semiconductor chip, and without degrading efficiency. A micro power converter comprises a micro transformer composed of a planar transformer having a structure including a conductor wound on and through a planar magnetic core, and a semiconductor chip including semiconductor switches S1, S2, and a control circuit for controlling the switches. By constructing a flyback transformer using a micro transformer composed of a planar transformer, a micro power converter of a step-up and step-down type is provided having two semiconductor switches and an overall size comparable to a conventional micro power converter.Type: ApplicationFiled: December 1, 2008Publication date: June 11, 2009Applicant: Fuji Electric Device Technology Co., LtdInventor: Satoshi Sugahara
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Patent number: 7545013Abstract: A nonvolatilely reconfigurable logical circuit is built. It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET. By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/“1”/“0”. Since it is possible to constitute the logical function by a small number of non-volatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.Type: GrantFiled: March 26, 2004Date of Patent: June 9, 2009Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Tomohiro Matsuno, Masaaki Tanaka
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Patent number: 7528428Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the (ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).Type: GrantFiled: January 23, 2004Date of Patent: May 5, 2009Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Masaaki Tanaka
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Publication number: 20090096436Abstract: A DC-DC converter includes a series circuit of a main switch and a choke coil and an output capacitor connected to one end of the series circuit and outputs a DC voltage from the one end of the series circuit. A first MOS transistor is connected in parallel to the series circuit and a second MOS transistor is connected in parallel to the output capacitor. A control circuit controls the gate voltages of the first MOS transistor and/or the second MOS transistor so that the first MOS transistor and/or the second MOS transistor outputs a changed target output voltage, whereby the output voltage is made equal to the target voltage at high speed.Type: ApplicationFiled: June 3, 2008Publication date: April 16, 2009Applicant: Fuji Electric Device Technology Co., LtdInventors: Satoshi SUGAHARA, Kouhei Yamada, Tetsuya Kawashima, Akira Yamazaki
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Publication number: 20090039401Abstract: A logic circuit that can reconfigure its functions in a nonvolatile manner and a single-electron transistor to be used in the logic circuits are provided. The logic circuit has a single-electron spin transistor that includes: a source; a drain; an island that is provided between the source and the drain, and has tunnel junctions between the island and the source and drain; and a gate that is capacitively coupled to the island. In this logic circuit, at least one of the source, the drain, and the island includes a ferromagnetic material having a variable magnetization direction.Type: ApplicationFiled: February 2, 2006Publication date: February 12, 2009Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Masaaki Tanaka, Satoshi Sugahara, Hai Nam Pham
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Publication number: 20080308853Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.Type: ApplicationFiled: November 1, 2007Publication date: December 18, 2008Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Satoshi Sugahara, Masaaki Tanaka