Abstract: Control circuit and method for controlling a switching power supply, which regulates its output voltage using pulse-width modulation (PWM) that switches on and off a main switch with a PWM signal (VCONT) at an adjusted ON-period ratio of the main switch. The control circuit includes an error signal amplifier circuit that compares the output voltage with a reference voltage and outputs an error signal VE based on the comparison. The control circuit also includes an ON-period adjusting circuit that starts generating a PWM signal (VCONT) in every cycle based on a pulse VPULSE, the period thereof being fixed, and adjusts the HIGH-period of the PWM signal (VCONT) based on the output voltage of the error signal VE. As a result, the control circuit widens the HIGH-period ratio range or the LOW-period ratio range of the PWM signal greatly.

Abstract: A switching power supply system has a control circuit that controls an output voltage by causing a switching device to turn ON and OFF. The control circuit includes a control pulse supplying unit that supplies a pulsed signal that_keeps the switching device turned-ON and -OFF. A protection circuit shuts down the switching power supply system upon occurrence of an abnormality. A delay circuit produces a delay signal that delays by a specified time duration the termination of a state of the pulsed signal in which the pulsed signal keeps the switching device turned-ON. The protection circuit is responsive to the pulsed signal or the delay signal to switch between an operation state and a stand-by state.

Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.

Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

Abstract: A DC-DC converter of a synchronous rectifier type, a control circuit thereof and control method thereof, facilitates detecting and interrupting negative inductor current IL with low power consumption, high accuracy and a simple configuration and facilitates improving the efficiency under a light load. An ON-period decision circuit determines whether an ON-period of the synchronous rectifier switch is too long or too short. An ON-period adjustment circuit generates a signal for adjusting the ON-period, during which the synchronous rectifier switch is ON, based on the decision of the ON-period decision part. A delay circuit adjusts the length of the delay, from the time when a signal changing the ON and OFF states of the synchronous rectifier switch changes to ON, to the time when the synchronous rectifier switch is forcibly turned off based on the adjusting signal.

Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the (ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).

Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.

Abstract: A nonvolatilely reconfigurable logical circuit is built It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET. By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/“1”/“0”. Since it is possible to constitute the logical function by a small number of non-volatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.

Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

Abstract: A gallium nitride-based compound semiconductor chip comprises a gallium nitride substrate having a (0001) facet of a wurtzite type crystal structure as a principal facet and a gallium nitride-based compound semiconductor crystal formed on the gallium nitride substrate, wherein: the gallium nitride-based compound semiconductor chip has a plurality of division facets and at least one of the plurality of division facets of the gallium nitride-based compound semiconductor chip is in a cleave facet direction of the gallium nitride substrate.

Abstract: A DC-DC converter facilitates preventing switching noises, caused by the switching of a main switching transistor and its driver, from affecting a control circuit adversely and securing stable operations of the converter. Specifically, the DC-DC converter includes a feed line LS1 for the main circuit, a ground line LG1 for the main circuit, a positive feed line LS2 for the control circuit, a negative feed line LG2 for the control circuit 3, an insulation resistance Rd1 connected to the feed line LS1 or to the feed line LS2, (or) an insulation resistance Rd2 connected to the ground line LG1 or to the feed line LG2, and, if necessary, a filter capacitor Cd connected in parallel to the control circuit 3.

Abstract: A gallium nitride type compound semiconductor light-emitting device of the present invention includes: a substrate; a buffer layer, formed on the substrate, having a thick region and a thin region in terms of a thickness taking a surface of the substrate as a reference level; and a semiconductor layered structure, formed on the buffer layer, at least including an undoped gallium nitride type compound semiconductor layer, a gallium nitride type compound semiconductor active layer, and a P-type gallium nitride type compound semiconductor cladding layer.

Abstract: A dry etching method for etching a gallium nitride type compound semiconductor is disclosed. The method uses a mixed gas including silicon tetrachloride (SiCl.sub.4) gas and chlorine (Cl.sub.2) gas as an etching gas in a reactive ion etching.

Abstract: A quantum wire structure includes a first layer having a thickness sufficiently smaller than a de Broglie wavelength of an electron wave in a medium, a second layer and a third layer which are disposed on and under the first layer and respectively have a forbidden band width larger than that of the first layer, wherein the first layer has a region with a relatively small curvature and a region with a relatively large curvature in its cross-section, and a width of the region with a relatively small curvature is 50 nm or less.

Abstract: A semiconductor laser of the present invention includes: a semiconductor substrate, a multi-layered structure formed on the semiconductor substrate and a current and light confining section formed on the multi-layered structure, wherein the current and light confining section includes at least two multi-layered current and light confining portions each having a laser beam transmission layer and a laser beam absorption layer formed on the laser beam transmission layer, and at least one stripe groove which spatially separates the at least two current and light confining portions; wherein an equivalent refractive index in the multi-layered current and light confining portions with respect to a laser beam in a fundamental transverse mode is made smaller than that within the stripe groove; wherein the multi-layered structure includes an active layer, and the active layer has a region positioned below the stripe groove of the current and light confining section and regions positioned below a respective one of the m

Abstract: A semiconductor laser device with window regions according to the present invention is provided, in which a double hetero structure including cladding layers and an active layer sandwiched by the cladding layers is formed on a semiconductor substrate, the double hetero structure is buried in burying layers with a bandgap larger than that of the active layer, and the burying layers form window regions situated at both end facets of the double hetero structure, wherein the window regions have a waveguide structure including a plurality of semiconductor layers with different bandgaps.

Abstract: A semiconductor device includes a multiple layer structure including a substantially flat active layer, and a first semiconductor layer and a second semiconductor layer adjacent to each other, the semiconductor layers having a corrugation at an interface therebetween; and a generating device which is connected to the multiple layer structure. An electromagnetic field intensity distribution is generated by use of the generating device in a waveguide region including the active layer, and the active layer includes a gain distribution having a distribution pattern corresponding to the corrugation. The multiple layer structure is produced by forming the corrugation on an upper surface of the first semiconductor layer, and forming the rest of the multiple layer structure including the second semiconductor layer and the active layer by using a vapor phase growth method once so as to make the active layer substantially flat. Then, the generating device is formed to be in contact with the multiple layer structure.

Abstract: A distributed feedback semiconductor laser device comprising a current blocking structure having a stripe groove, and a diffraction grating formed in the bottom of the stripe groove. The current blocking structure is formed over an active layer for laser oscillation, and it includes an etch stop layer against a groove etching in a lower potion of the current blocking structure. The refractive index distribution in transverse directions inside the stripe groove is controlled by the thickness of the optical guiding layer, enabling oscillation of the fundamental transverse mode.