Patents by Inventor Satoshi Tamura

Satoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10999878
    Abstract: A communication system capable of improving signal processing efficiency even when a plurality of connections are established is provided. A communication system according to the present invention includes a user plane PGW (14) configured to connect to a PDN, a user plane SGW (12) configured to relay user plane data between the user plane PGW (14) and a base station (34), and a control plane SGW (30). Further, the communication system includes a control apparatus (32) configured to, when a plurality of connections are established for the communication terminal (36), transmit information indicating that the user plane PGW (14) and the user plane SGW (12) can be integrally configured to the control plane SGW (30) for each of the plurality of connections.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 4, 2021
    Assignee: NEC CORPORATION
    Inventors: Satoshi Kuroda, Toshiyuki Tamura, Kazuo Watanabe
  • Patent number: 10982901
    Abstract: A drying system includes a nozzle attached to an air supply duct of a drying chamber that blows out heated air inside the duct toward an object to be dried inside the chamber. The nozzle includes a horn-shaped inner-side surface made of pairs of first and second inner-side surfaces that respectively face each other in first and second directions, an opening width of the second surfaces in the second direction gradually increasing forward in a direction in which the air is blown and being 2 to 25 times inclusive larger than an opening width in the first direction. The drying system includes: the duct with the nozzles; a feeding device feeding air to the duct; and a heating device heats the fed air. The feeding device feeds air to the duct such that the air blown out from the nozzle spreads more in the first direction than in the second.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 20, 2021
    Assignee: TRINITY INDUSTRIAL CORPORATION
    Inventors: Manabu Hakata, Yasushi Kondo, Keiichi Suzuki, Kimihiko Sugiura, Satoshi Tamura
  • Patent number: 10941019
    Abstract: According to one embodiment, a user detection system includes a camera, a boundary detector, a user detector and a controller. The camera is installed in a peripheral region of a door, and captures a running region when opening or closing the door and a region near the door. The boundary detector detects a boundary between a first structure and a second structure in the region near the door based on an image captured by the camera. The user detector detects whether there is a user in the running region based on a result detected by the boundary detector. The controller controls an open/close operation of the door based on a result detected by the user detector.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Shuhei Noda, Kentaro Yokoi, Satoshi Tamura, Sayumi Kimura
  • Publication number: 20210057564
    Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: Hidekazu UMEDA, Kazuhiro KAIBARA, Satoshi TAMURA
  • Publication number: 20210005742
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Panasonic Corporation
    Inventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
  • Publication number: 20200411679
    Abstract: A nitride semiconductor device includes: a substrate having a first main surface and a second main surface; a first nitride semiconductor layer of a first conductivity type provided above the first main surface; a second nitride semiconductor layer of a second conductivity type provided above the first nitride semiconductor layer; a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer provided above the second nitride semiconductor layer and on an inner surface of the first opening; a gate electrode provided above the electron transport layer and covering the first opening; a source electrode connected to the second nitride semiconductor layer; a drain electrode provided on a second main surface-side of the substrate; and a high-resistance layer provided between the second nitride semiconductor layer and the electron transport layer in the first opening, the high-resistance layer including a nitride semiconductor.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: Masahiro OGAWA, Daisuke SHIBATA, Satoshi TAMURA
  • Publication number: 20200411706
    Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.
    Type: Application
    Filed: January 15, 2019
    Publication date: December 31, 2020
    Applicant: Panasonic Corporation
    Inventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
  • Patent number: 10868167
    Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 15, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidekazu Umeda, Kazuhiro Kaibara, Satoshi Tamura
  • Patent number: 10818815
    Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 27, 2020
    Assignee: PANASONIC CORPORATION
    Inventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
  • Publication number: 20200312964
    Abstract: A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.
    Type: Application
    Filed: August 31, 2018
    Publication date: October 1, 2020
    Applicant: Panasonic Corporation
    Inventors: Daisuke Shibata, Satoshi Tamura, Nanako Hirashita
  • Publication number: 20200299104
    Abstract: According to one embodiment, an elevator passenger detection system comprises an image capturing unit, a detection area setting unit, and a detection processing unit. The image capturing unit captures an image in a predetermined range including a vicinity of a doorway at which a door is opened or closed, from an inside of a car. The detection area setting unit sets a detection area on a front return panel provided on at least one of sides of a doorway of the car, on the captured image obtained by the image capturing unit. The detection processing unit detects presence of a passenger or an object, based on the image in the detection area set by the detection area setting unit.
    Type: Application
    Filed: December 2, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Shuhei NODA, Kentaro YOKOI, Sayumi KIMURA, Satoshi TAMURA
  • Patent number: 10706553
    Abstract: According to one embodiment, an image detection system includes an imaging apparatus, an edge extraction unit, a specific-edge extraction unit, a candidate area extraction unit, and a to-be-detected area determination unit. The edge extraction unit extracts edges each representing a boundary line between areas with different features. The specific-edge extraction unit extracts specific edges including at least remaining edges present in background image and input image. The candidate area extraction unit extracts candidate areas for a preset area to be detected. The to-be-detected area determination unit determines the area to be detected from candidate areas extracted.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Kentaro Yokoi, Shuhei Noda, Satoshi Tamura, Sayumi Kimura
  • Patent number: 10690411
    Abstract: A circulation channel circularly supplying air heated by a burner is connected to a drying chamber into which a painted workpiece is supplied. The circulation channel includes a flame holding cylinder surrounding a flame of the burner and a casing surrounding the flame holding cylinder from outside and protrudes further than the flame holding cylinder toward a front end side, opposite to a side of the burner, of the flame holding cylinder. The casing includes a low temperature air inlet port that introduces low temperature air from outside into the casing, an exhaust port that exhausts high temperature air heated by the burner and the low temperature air to the circulation channel, and a mixing mechanism that is formed in the casing and mixes the high temperature air and the low temperature air before the high temperature air and the low temperature air are exhausted from the exhaust port.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 23, 2020
    Assignee: TRINITY INDUSTRIAL CORPORATION
    Inventor: Satoshi Tamura
  • Patent number: 10686042
    Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 16, 2020
    Assignee: PANASONIC CORPORATION
    Inventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
  • Publication number: 20200033058
    Abstract: A drying system includes a nozzle attached to an air supply duct of a drying chamber that blows out heated air inside the duct toward an object to be dried inside the chamber. The nozzle includes a horn-shaped inner-side surface made of pairs of first and second inner-side surfaces that respectively face each other in first and second directions, an opening width of the second surfaces in the second direction gradually increasing forward in a direction in which the air is blown and being 2 to 25 times inclusive larger than an opening width in the first direction. The drying system includes: the duct with the nozzles; a feeding device feeding air to the duct; and a heating device heats the fed air. The feeding device feeds air to the duct such that the air blown out from the nozzle spreads more in the first direction than in the second.
    Type: Application
    Filed: November 6, 2017
    Publication date: January 30, 2020
    Applicant: TRINITY INDUSTRIAL CORPORATION
    Inventors: Manabu HAKATA, Yasushi KONDO, Keiichi SUZUKI, Kimihiko SUGIURA, Satoshi TAMURA
  • Patent number: 10529843
    Abstract: A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: Panasonic Corporation
    Inventors: Daisuke Shibata, Satoshi Tamura, Masahiro Ishida
  • Patent number: 10510656
    Abstract: A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: December 17, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura
  • Publication number: 20190326465
    Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
  • Patent number: 10367401
    Abstract: In a 4-pole, 6-slot, 18-segment electric motor, one forward winding coil (91) and two reverse winding coils (92, 93) are wound on each tooth (12). When the forward winding coils are formed of coils corresponding to a U phase, a V phase, and a W phase and the reverse winding coils are formed of coils corresponding to a “?U” phase, a “?V” phase, and a “?W” phase, the coils, which correspond to a U phase, a “?W” phase, a “?W” phase, a V phase, a “?U” phase, a “?U” phase, a W phase, a “?V” phase, and a “?V” phase, are electrically connected in this order between the adjacent segments.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 30, 2019
    Assignee: Mitsuba Corporation
    Inventors: Natsumi Tamura, Hiroto Tanaka, Teppei Tokizaki, Satoshi Tamura
  • Patent number: 10355143
    Abstract: A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 16, 2019
    Assignee: PANASONIC CORPORATION
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda