Patents by Inventor Satoshi Tamura

Satoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180012960
    Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Inventors: Yusuke KINOSHITA, Hidekazu UMEDA, Satoshi TAMURA
  • Patent number: 9842905
    Abstract: A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 ?m.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: December 12, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Yoshiharu Anda, Tetsuzo Ueda
  • Patent number: 9837496
    Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0?p+q?1, 0?p, and 0?q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0?r+s?1, 0?r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0?t+u?1, 0?t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0?x+y?1, 0?x, and 0?y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Tetsuzo Ueda
  • Publication number: 20170221814
    Abstract: A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.
    Type: Application
    Filed: July 1, 2015
    Publication date: August 3, 2017
    Inventors: Yusuke KINOSHITA, Satoshi TAMURA
  • Publication number: 20170104395
    Abstract: An electric motor includes: brushes (31) that are brought into sliding contact with a commutator of an armature that is fixed to a rotation shaft and feeds electric power; a brush holder stay (33) that supports the brushes (31) via brush holders (41); noise prevention elements (110) that are electrically connected to the brushes (31); and terminals (130) and jump wires (141) that electrically connect between the brush holders (41) and the noise prevention elements (110), wherein first connection portions, which connect between the noise prevention elements (110) and the terminals (130), and second connection portions, which connect between the terminals (130) and the jump wires (141), are both disposed only on a first surface (S1) of the brush holder stay (33).
    Type: Application
    Filed: May 13, 2015
    Publication date: April 13, 2017
    Inventors: Natsumi TAMURA, Tomoo IIJIMA, Teppei TOKIZAKI, Satoshi TAMURA
  • Publication number: 20160352176
    Abstract: An armature core (8A) includes a plurality of teeth (12) that radially extend. A plurality of coils (91), (92), and (93) are wound in a concentrated winding manner on a winding drum portion (12a) of each tooth; a winding wire (14) of a lowermost side of at least a first-layer coil is wound so as to come into close contact with a winding surface of a base end side of the winding drum portion; a second-layer coil, which is to be wound later, is wound so that at least a part of the second-layer coil overlaps the first-layer coil; and a step (12a1) as a regulating portion, which regulates the positional deviation of the winding wire of the lowermost side of the first-layer coil in an extending direction of the winding drum portion, is provided on at least a part of the winding surface for the first-layer coil on an outer periphery of the winding drum portion.
    Type: Application
    Filed: March 4, 2015
    Publication date: December 1, 2016
    Inventors: Teppei Tokizaki, Akio Hoshino, Natsumi Tamura, Satoshi Tamura
  • Publication number: 20160344273
    Abstract: In a 4-pole, 6-slot, 18-segment electric motor, one forward winding coil (91) and two reverse winding coils (92, 93) are wound on each tooth (12). When the forward winding coils are formed of coils corresponding to a U phase, a V phase, and a W phase and the reverse winding coils are formed of coils corresponding to a “?U” phase, a “?V” phase, and a “?W” phase, the coils, which correspond to a U phase, a “?W” phase, a “?W” phase, a V phase, a “?U” phase, a “?U” phase, a W phase, a “?V” phase, and a “?V” phase, are electrically connected in this order between the adjacent segments.
    Type: Application
    Filed: March 5, 2015
    Publication date: November 24, 2016
    Applicants: Mitsuba Corporation, Mitsuba Corporation
    Inventors: Natsumi Tamura, Hiroto Tanaka, Teppei Tokizaki, Satoshi Tamura
  • Patent number: 9484342
    Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 1, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroyuki Handa, Hidekazu Umeda, Satoshi Tamura, Tetsuzo Ueda
  • Patent number: 9449761
    Abstract: A polypropylene for a film capacitor or a polypropylene sheet for a film capacitor which exhibits excellent stretchability when stretched into a film and provides a film having high breakdown voltage and small thermal shrinkage ratio, and which is suitable for a polypropylene film for a film capacitor and a film capacitor comprising the film. The polypropylene for a film capacitor of the present invention is obtained by irradiating a propylene homopolymer with a radiation with an absorbed dose of 0.1 to 500 kGy, the propylene homopolymer having (1) a melt flow rate (MFR) within a range of 1 to 10 g/10 min as determined at 230° C. under a load of 2.16 kg in accordance with ASTM D1238, (2) an isotactic pentad fraction (mmmm fraction) of not less than 94% as determined using 13C-NMR, (3) an ash amount of not more than 30 ppm as obtained by completely burning the propylene homopolymer in air, and (4) a chlorine amount of not more than 10 ppm as determined by ion chromatography.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: September 20, 2016
    Assignee: PRIME POLYMER CO., LTD.
    Inventors: Noriko Tan, Satoshi Tamura
  • Publication number: 20160064376
    Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: HIROYUKI HANDA, HIDEKAZU UMEDA, SATOSHI TAMURA, TETSUZO UEDA
  • Publication number: 20160056245
    Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0?p+q?1, 0?p, and 0?q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0?r+s?1, 0?r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0?t+u?1, 0?t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0?x+y?1, 0?y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: YUSUKE KINOSHITA, SATOSHI TAMURA, TETSUZO UEDA
  • Publication number: 20150274908
    Abstract: [Problem] To provide polypropylene for a microporous film having excellent heat resistance and strength. [Solution] Polypropylene for a microporous film satisfying the following requirements (1) and (2): (1) the weight-average molecular weight (Mw) value, as determined by gel permeation chromatography (GPC), is not less than 100,000 but less than 800,000, the value (Mw/Mn) obtained by dividing the weight-average molecular weight by the number-average molecular weight is more than 7.0 but not more than 12.0, and the value (Mz/Mw) obtained by dividing the Z-average molecular weight by the weight-average molecular weight is not less than 3.8 but not more than 9.0, and (2) the mesopentad fraction, as measured by 13C-NMR (nuclear magnetic resonance method), is not less than 95.5%.
    Type: Application
    Filed: October 23, 2013
    Publication date: October 1, 2015
    Applicant: Prime Polymer Co., Ltd.
    Inventors: Yoshio Yanagishita, Chikara Satou, Satoshi Tamura, Katsutoshi Ohta
  • Publication number: 20150179741
    Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 25, 2015
    Inventors: HIDEKAZU UMEDA, KAZUHIRO KAIBARA, SATOSHI TAMURA
  • Patent number: 9009507
    Abstract: According to one embodiment, a method controls an apparatus including a sensor which detects an open/close state of a cover, and an power manager which performs power management of the apparatus in accordance with a ordinary state and a power-saving state. The method includes notifying turning on the apparatus in order to change the apparatus to the ordinary state, if the power manager is notified a second notifying and the sensor detects that the cover is opened, and performing an power management corresponding to the power-saving state, if the power manager is notified a first notifying, or if the power manager is notified the second notifying and the sensor detects that the cover is closed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Tamura
  • Patent number: 8916644
    Abstract: [Object] To provide a polypropylene resin composition for use in the formation of a microporous membrane having excellent heat resistance and strength. [Solution] A polypropylene resin composition for use in the formation of a microporous membrane according to the present invention comprises as an essential component an ultra-high-molecular-weight propylene homopolymer (A) that satisfies the following requirements (1) to (4): (1) the intrinsic viscosity [?] is 7 dl/g or more and less than 25 dl/g; (2) the mesopentad fraction ranges from 90.0% to 99.5%; (3) the melting point ranges from 153° C. to 167° C.; and (4) in an elution temperature-elution volume curve measured by temperature-rising elution fractionation (TREF), the maximum peak has a peak top temperature in the range of 116° C. to 125° C. and a half-width of 7.0° C. or less.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: December 23, 2014
    Assignees: Toray Battery Separator Film Co., Ltd, Prime Polymer Co., Ltd.
    Inventors: Satoshi Tamura, Ryoichi Tsunori
  • Patent number: 8901240
    Abstract: [Object] To provide a polypropylene resin composition for use in the formation of a microporous membrane having excellent heat resistance and low thermal shrinkage ratio. [Solution] A polypropylene resin composition for use in the formation of a microporous membrane according to the present invention comprises as an essential component a propylene homopolymer (A) that satisfies the following requirements (1) to (4) and (7): (1) the intrinsic viscosity [?] is 1 dl/g or more and less than 7 dl/g; (2) the mesopentad fraction ranges from 94.0% to 99.5%; (3) the integral elution volume during heating to 100° C. is 10% or less; (4) the melting point ranges from 153° C. to 167° C.; and (7) in an elution temperature-elution volume curve, the maximum peak has a peak top temperature in the range of 105° C. to 130° C. and a half-width of 7.0° C. or less.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: December 2, 2014
    Assignees: Mitsui Chemicals Inc., Prime Polymer Co., Ltd.
    Inventors: Satoshi Tamura, Keita Itakura, Ryoichi Tsunori, Satoshi Hashizume
  • Patent number: 8791505
    Abstract: A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Yoshiharu Anda, Tetsuzo Ueda
  • Publication number: 20140103459
    Abstract: A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 ?m.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Yusuke KINOSHITA, Satoshi TAMURA, Yoshiharu ANDA, Tetsuzo UEDA
  • Patent number: D777214
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 24, 2017
    Assignee: Mitsubishi Mahindra Agricultural Machinery Co., Ltd.
    Inventors: Yoshiyuki Moritaka, Yukihiro Komatsu, Hiromu Kadowaki, Koji Nakashima, Satoshi Tamura, Yasuhiro Kodama, Keiichi Baba, Toshinobu Watanabe, Kenshiro Yakushiji, Hirotaka Yato, Akira Kurisu
  • Patent number: D777215
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 24, 2017
    Assignee: Mitsubishi Mahindra Agricultural Machinery Co., Ltd.
    Inventors: Yoshiyuki Moritaka, Yukihiro Komatsu, Hiromu Kadowaki, Koji Nakashima, Satoshi Tamura, Yasuhiro Kodama, Keiichi Baba, Toshinobu Watanabe, Kenshiro Yakushiji, Hirotaka Yato, Akira Kurisu