Patents by Inventor Sau C. Wong
Sau C. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7554844Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.Type: GrantFiled: October 22, 2007Date of Patent: June 30, 2009Assignee: SanDisk CorporationInventors: Carl W. Werner, Andreas M. Haeberli, Leon Sea Jiunn Wong, Cheng-Yuan Michael Wang, Hock C. So, Sau C. Wong
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Patent number: 7397697Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process checks whether a threshold voltage is in a forbidden zone. Alternately, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be performed in response to detecting a threshold voltage in a forbidden zone or periodically.Type: GrantFiled: January 5, 2007Date of Patent: July 8, 2008Assignee: SanDisk CorporationInventors: Hock C. So, Sau C. Wong
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Patent number: 7349255Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.Type: GrantFiled: July 18, 2005Date of Patent: March 25, 2008Assignee: SanDisk CorporationInventor: Sau C. Wong
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Patent number: 7298670Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.Type: GrantFiled: July 27, 2006Date of Patent: November 20, 2007Assignee: SanDisk CorporationInventors: Carl W. Werner, Andreas M. Haeberli, Leon Sea Jiunn Wong, Cheng-Yuan Michael Wang, Hock C. So, Sau C. Wong
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Patent number: 7268809Abstract: A digital imaging system uses a high density, high speed analog/multi-level memory to temporarily store image data at high rates for extended periods of time. A portion of the stored data is transmitted for image processing and compression. When image processing and compression on the data are completed, another portion of the stored data is transmitted for processing. As a result, high speed image capture for extended periods is possible because the processing speed of the image processing and compression no longer limit the time required between high speed bursts or the length of a high speed burst.Type: GrantFiled: September 23, 1998Date of Patent: September 11, 2007Assignee: San Disk CorporationInventors: Sau C. Wong, Leo Petropoulos
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Patent number: 7170781Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.Type: GrantFiled: April 7, 2005Date of Patent: January 30, 2007Assignee: SanDisk CorporationInventors: Hock C. So, Sau C. Wong
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Patent number: 7106632Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.Type: GrantFiled: February 5, 2003Date of Patent: September 12, 2006Assignee: SanDisk CorporationInventors: Carl W. Werner, Andreas M. Haeberli, Leon Sea Jiunn Wong, Cheng-Yuan Michael Wang, Hock C. So, Sau C. Wong
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Patent number: 7080192Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased, after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.Type: GrantFiled: October 2, 2003Date of Patent: July 18, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Sau C. Wong
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Patent number: 6944058Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.Type: GrantFiled: June 13, 2003Date of Patent: September 13, 2005Assignee: SanDisk CorporationInventor: Sau C. Wong
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Patent number: 6898117Abstract: A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation.Type: GrantFiled: October 18, 2001Date of Patent: May 24, 2005Assignee: SanDisk CorporationInventors: Hock C. So, Sau C. Wong
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Patent number: 6760068Abstract: A method and system using a sensor array includes a programmable analog/multi-level memory array for modifying individual outputs from elements in the sensor array in order to obtain a desired sensor array output. The memory array can be programmed with data corresponding to desired modifications, such as low and high offset voltage correction, low gain correction, and gamma correction. Consequently, by utilizing arithmetic circuits, the adverse effects of corrupted elements in a sensor can be corrected by re-programming the memory array with different modification data as the need arises.Type: GrantFiled: December 31, 1998Date of Patent: July 6, 2004Assignee: SanDisk CorporationInventors: Leo Petropoulos, Sau C. Wong
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Patent number: 6760262Abstract: An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.Type: GrantFiled: March 4, 2003Date of Patent: July 6, 2004Assignee: SanDisk CorporationInventors: Andreas M. Haeberli, Sau C. Wong, Hock C. So, Carl W. Werner, Cheng-Yuan Michael Wang, Leon Sea Jiunn Wong
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Patent number: 6662263Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased; after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.Type: GrantFiled: March 3, 2000Date of Patent: December 9, 2003Assignee: Multi Level Memory TechnologyInventor: Sau C. Wong
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Publication number: 20030206469Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventor: Sau C. Wong
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Publication number: 20030202389Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.Type: ApplicationFiled: February 5, 2003Publication date: October 30, 2003Applicant: SanDisk Corporation, a Delaware CorporationInventors: Carl W. Werner, Andreas M. Haeberli, Leon Sea Jiunn Wong, Cheng-Yuan Michael Wang, Hock C. So, Sau C. Wong
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Patent number: 6624773Abstract: A scrambling or encryption method involves analog-to-digital, digital-to-analog, analog-to-analog or digital-to-digital conversions that are constructed from one or more analog-to-digital or digital-to-analog conversions. For example, encryption of an analog signal converts the analog signal to an intermediate digital signal that is converted back into a scrambled analog signal. Encryption of a digital signal converts the digital signal to an intermediate analog signal that is converted back into an encrypted digital signal. The conversions between analog form and digital form and back can be repeated. A codec scrambling/descrambling and encryption/decryption implements one or more different analog-to-digital conversions and one or more digital-to-analog conversions. One embodiment of the codec includes a programmable conversion array that includes an array of transistors such as floating gate transistors in memory cells.Type: GrantFiled: October 4, 2002Date of Patent: September 23, 2003Assignee: SanDisk CorporationInventor: Sau C. Wong
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Publication number: 20030161171Abstract: An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.Type: ApplicationFiled: March 4, 2003Publication date: August 28, 2003Applicant: INVOX TECHNOLOGY, a California CorporationInventors: Andreas M. Haeberli, Sau C. Wong, Hock C. So, Carl W. Werner, Cheng-Yuan Michael Wang, Leon Sea Jiunn Wong
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Patent number: 6606267Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.Type: GrantFiled: October 18, 2001Date of Patent: August 12, 2003Assignee: SanDisk CorporationInventor: Sau C. Wong
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Patent number: 6594036Abstract: A digital imaging system uses an analog/multi-level memory to store image data. The stored analog/multi-level data can then be accessed directly by an analog device or the data can be accessed by an A/D converter for conversion to a digital format. The digital data is then routed to any number of desired digital devices. By using an analog/multi-level memory instead of a digital memory to store image data, problems associated with storing large amounts of digital data are minimized or eliminated, such as loss of information from image compression and high costs of large digital memories and signal processing and compression circuits.Type: GrantFiled: May 28, 1998Date of Patent: July 15, 2003Assignee: SanDisk CorporationInventors: Sau C. Wong, Leo Petropoulos, John H. Chan
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Publication number: 20030090580Abstract: A method and system using a sensor array includes a programmable analog/multi-level memory array for modifying individual outputs from elements in the sensor array in order to obtain a desired sensor array output. The memory array can be programmed with data corresponding to desired modifications, such as low and high offset voltage correction, low gain correction, and gamma correction. Consequently, by utilizing arithmetic circuits, the adverse effects of corrupted elements in a sensor can be corrected by re-programming the memory array with different modification data as the need arises.Type: ApplicationFiled: December 31, 1998Publication date: May 15, 2003Inventors: LEO PETROPOULOS, SAU C. WONG