Abstract: An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Abstract: A digital imaging system uses a high density, high speed analog/multi-level memory to temporarily store image data at high rates for extended periods of time. A portion of the stored data is transmitted for image processing and compression. When image processing and compression on the data are completed, another portion of the stored data is transmitted for processing. As a result, high speed image capture for extended periods is possible because the processing speed of the image processing and compression no longer limit the time required between high speed bursts or the length of a high speed burst.

Abstract: A scrambling or encryption method involves analog-to-digital, digital-to-analog, analog-to-analog or digital-to-digital conversions that are constructed from one or more analog-to-digital or digital-to-analog conversions. For example, encryption of an analog signal converts the analog signal to an intermediate digital signal that is converted back into a scrambled analog signal. Encryption of a digital signal converts the digital signal to an intermediate analog signal that is converted back into an encrypted digital signal. The conversions between analog form and digital form and back can be repeated. A codec scrambling/descrambling and encryption/decryption implements one or more different analog-to-digital conversions and one or more digital-to-analog conversions. One embodiment of the codec includes a programmable conversion array that includes an array of transistors such as floating gate transistors in memory cells.

Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.

Abstract: A scrambling or encryption method involves analog-to-digital, digital-to-analog, analog-to-analog or digital-to-digital conversions that are constructed from one or more analog-to-digital or digital-to-analog conversions. For example, encryption of an analog signal converts the analog signal to an intermediate digital signal that is converted back into a scrambled analog signal. Encryption of a digital signal converts the digital signal to an intermediate analog signal that is converted back into an encrypted digital signal. The conversions between analog form and digital form and back can be repeated. A codec scrambling/descrambling and encryption/decryption implements one or more different analog-to-digital conversions and one or more digital-to-analog conversions. One embodiment of the codec includes a programmable conversion array that includes an array of transistors such as floating gate transistors in memory cells.

Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.

Abstract: An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Abstract: An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Abstract: A non-volatile Flash memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. The memory has a row based sector architecture, i.e., sectors that contain one or more complete rows of memory cells. During an erase operation, an erase voltage applied to the source lines for one or more rows corresponding to a sector does not affect write or read operations being performed in other sectors, i.e., other rows. Similarly, voltages applied to row lines for access to a memory cell have no effect on the erase operation being performed in another sector. A column line voltage applied for access to a memory cell has little affect on the erase operation. The memory can implement a look-ahead erase for a continuous reading or writing operation.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.

Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.

Abstract: Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: An integrated circuit stores analog or digital information, or both, in memory cells (416). The memory cells provide analog or multilevel storage. Analog information is provided through an analog signal input (405), and digital information is provided through a digital signal input (407). A scheme for storing digital information is consistent with the scheme used to store analog information. Data is retrieved from the memory cells, and output to the analog or digital signal output (454, 463) depending on the type of data. A digital reference generator reference generator (425) generates various analog equivalent voltages for the digital signal input.

Abstract: Level shifter circuits are used to configure analog or multilevel memory cells. A level shifter circuit generates an output voltage that is above the input voltage by an offset voltage value. The magnitude of this offset voltage or the relationship between the input and output voltages of the level shifter is adjustable or programmably selectable. Adjustments can be made after the integrated circuits is fabricated and packaged. Adjustments are made by configuring bits of data in the integrated circuit to indicate the offset voltage or other parameters. These configuration bits are implemented using latches, flip-flops, registers, memory cells, or other storage circuits.

Abstract: An integrated circuit memory is capable of storing analog information without the need for A/D conversion. Samples of a analog signal input are stored in nonvolatile memory cells. The integrated circuit is also capable of storing digital information in digital form. The sampling rate at which the analog signal input is sampled is user selectable. An internal signal path of the integrated circuit memory is differential, which enhances the precision with which the analog signal is stored in the memory cells.

Abstract: Converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) use conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells. The array contains sets (for example, rows) of the memory cells where each memory cell in a set corresponds to a digital value and has a threshold voltage that is equal to the analog voltage mapped to the digital value. An ADC applies an analog input signal to the gates of reference cells in a set and generates a digital signal according to which of the memory cells conduct. The ADC does not require comparators and has a low circuit area, low power consumption, and high speed. A DAC selects a memory cell corresponding to a digital input value and reads the memory cell to generate an analog output signal equal to the threshold voltage of the memory cell. An ADC and a DAC can use the same conversion array to ensure that the ADC inverts the conversion that the DAC performs.