Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One write process applies a control gate voltage which provides a saturation threshold voltage near a target threshold voltage being written. A verify feedback process terminates the write when the target threshold voltage is reached. Variable write pulse widths, voltages, and loadline resistances reduce write time and further improve control of writing. The fast write time of EPROM and flash EPROM cells simplifies control of write processes and therefore reduces chip size and cost in applications such as sound recording. A read process reads a memory cell's threshold voltage using substantially the same circuit as used in the verify feedback process. One read process determines a memory cell's threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One write circuit to a control gate of a memory cell a voltage which after a long write time would saturate the threshold voltage of the memory cell near a target threshold voltage being written. One such write circuit includes a voltage shifter which generates the voltage to be applied to the control gate of the memory cell from an analog voltage representing a value to be written in the memory cell. A verify feedback circuit terminates the write when the target threshold voltage is reached. The write circuit uses variable write pulse widths, voltages, and loadline resistances to reduce write time and further improve control of writing. The fast write time of EPROM and flash EPROM cells simplifies control of write processes and therefore reduces chip size and cost in applications such as sound recording.

Abstract: An analog memory has comparison logic and a reference voltage generator built on-chip for testing of analog write and read processes. During a test, the reference voltage generator, which may be a resistor tree structure, provides a set of intermediate voltages. One of the intermediate voltages V.sub.IN is written to a selected memory cell. The comparison logic compares other intermediate voltages V.sub.H and V.sub.L to an analog output signal generated by reading the selected memory cell. A digital control signal from an external digital tester selects the levels of voltages V.sub.IN, V.sub.H, and V.sub.L. Typically, voltages V.sub.H and V.sub.L are equal V.sub.IN .+-..DELTA.V where .DELTA.V represents an acceptable resolution for stored analog data. If the signal from reading the selected memory cell falls within a desired range V.sub.IN .+-..DELTA.V, an output digital result signal is set; otherwise, the test result signal is cleared.

Abstract: A non-volatile analog memory contains multiple recording pipelines for sampling and storing values representing an analog signal and/or multiple playback pipelines for playing a recorded signal. Each recording pipeline includes a sample-and-hold circuit and a write circuit coupled to a memory array associated with that pipeline and is capable of write operations that overlap write operations of other recording pipelines. Each playback pipeline includes a read circuit and a sample-and-hold circuit coupled to an associated memory array and is capable of read operations that overlap read operations of other playback pipelines. The pipelines operate sequentially during recording or playback, and the number of pipelines is selected according to a desired sampling frequency. One embodiment provides a modular integrated circuit architecture which allows a user selected number of ICs to be connected together to handle a desired sampling frequency.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read process determines a memory cell's threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts. Another read process slowly ramps the source voltage of a memory cell and determines the cell's threshold voltage from the drain voltage of the memory cell. Still another read process connects a cascoding device to a memory cell and biases the memory cell in the linear region while the threshold voltage of the memory cell is determined from a voltage across a load which carries a current that mirrors the current through the memory cell. Read processes disclosed for analog memory cells also apply to binary memory cells, multilevel digital memory cells, and other applications which require precise reading of threshold voltages.