Abstract: Non-volatile memory cells in a sector of a memory array are selectively erased only when it is determined that the selected memory cells require erasing. A memory cell is selectively erased by applying two non-zero erase voltages to the cell, where the combination of the two erase voltages generates an electric field sufficient to induce Fowler-Nordheim tunneling and erase the cell. Memory cells not selected for erasing, either in the same sector or other sectors, have only one or none of the two erase voltages applied, which is insufficient to erase the unselected memory cells is a result, endurance of the non-volatile memory cells is improved because the memory cells are not subjected to repeated unnecessary erasing and programming operations.

Abstract: An analog-to-analog converter uses programmable conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells, with the type of conversion dependent on the threshold voltages of the cells. An analog input signal is applied to an analog-to-digital conversion array for conversion to a digital signal. The digital signal is applied to a digital-to-analog conversion array for conversion to an analog output signal. A memory cell in the digital-to-analog conversion array is selected corresponding to the digital signal and reads the memory cell to generate the analog output signal, which is equal to or has a one-to-one correspondence with the threshold voltage of the memory cell. The conversion arrays can be programmed with suitable threshold voltages to implement desired conversions, such as logarithmic conversion for voice applications or random conversions for signal encryption.

Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.

Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.

Abstract: Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb.

Abstract: A non-volatile, multi-bit-per-cell memory has a read circuit that includes a counter, a row line driver, and a sense circuit. During a read, the driver changes a read signal applied to the control gate of a selected memory cell being read. The counter simultaneously counts cycles of a clock signal. When the sense circuit sense a change in conductivity of the selected memory cell, the count in the counter indicates a multi-bit digital value corresponding to the threshold voltage of the selected memory cell and can be used to generate an output data signal. In one embodiment, the driver includes a digital-to-analog converter that generates the read signal. The converter is coupled to the counter so that a count from the counter controls the voltage of a read signal from the converter. The sense circuit can stop or disable the counter upon sensing a change in conductivity in a selected memory. The count is then output as a multi-bit digital value read from the selected memory cell.

Abstract: A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation.

Abstract: Continuous recording in a flash memory uses a look-ahead erase process that includes simultaneously writing data to a first sector in a first array while preparing (erasing and/or partially programming) a second sector in a second array. The second sector is ready for writing when a last datum fills the first sector and is immediately available for writing while a third sector is prepared. The look-ahead erase keeps preparing sectors so that writing can continue without interruptions for erase processes. Embodiments of the invention include integrated circuit memories having two or more memory arrays, each having a plurality of independently erasable sectors. Each time a sector is filled the write process switches to a sector in another array.

Abstract: A semiconductor memory includes a memory array and an address scrambler. The address scrambler maps sequential input addresses to non-sequential physical addresses for the memory array. In one embodiment, the address scramble includes circuitry that implements a one-to-one function mapping of the logical addresses to physical addresses. Alternatively, the address scrambler includes a pseudo-random series generator that generates a pseudo-random series for the physical addresses. In either case, consecutive memory accesses that would logically correspond to a single row or column are scattered among multiple rows and columns to diminish the length of a gap in a data sequence that would otherwise occur as a result of a defective row or column. For flash memory, the mapping can be restricted so that logical addresses for a sector map to physical address for the same or another sector.

Abstract: A non-volatile memory includes an array of memory cells that is partitioned into sectors with sources of memory cells in each sector coupled together but electrically isolated from sources of memory cells in other sectors. Each sector includes one or more rows of memory cells, and sources of memory cells in each row are coupled together by a source-line. During programming of a selected memory cell, a bias circuit grounds a source-line in the sector containing the selected memory cell and applies a bias voltage to the source-lines in the other sectors. The bias voltage reduces program disturb of memory cells that are connected to the same bit-line as the selected memory cell. The bias circuit is coupled to address decode circuitry that indicates which source-line should be grounded.

Abstract: A multilevel non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state or in the case of a flash memory, reading a sector of the memory, saving data from the sector in a buffer, erasing the sector, and rewriting the data from the buffer back in the sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months.

Abstract: A semiconductor memory stores multiple messages such as multiple sound clips and includes storage cells dedicated to storage of samples that constitute the messages and EOM cells dedicated to storage of marks identifying boundaries of the messages. In one embodiment, a set of the EOM cells are together in a row of an array, and each such EOM cell is associated with storage cells in the same column of the array. Each EOM cell is erased together with associated storage cells. To avoid overerase of EOM cells, a write process for a storage cell asserts a write pulse to the associated EOM cell. Write pulses resulting from writing of multiple storage cells associated with an EOM cell, change a threshold voltage of the EOM cell from the erased state to a partially programmed state. The EOM cell associated with a boundary of a message can be programmed to a state that differs from the partially programmed state.

Abstract: A memory architecture divides memory cells of a memory into multiple memory arrays where each memory array has local row and column lines that are directly coupled to memory cells in the memory array and electrically isolated from other arrays. Continuous global row and column lines cross the memory arrays. The memory additionally includes global decoders that apply operating voltages to the global lines corresponding to a selected memory cell being access. Local decoders decode bits from the address signal to select an array containing the selected memory cell and connect the global lines to the selected memory array. Other memory arrays are disconnected from the global lines to avoid disturbance that would result from the operating voltage being applied to unselected memory cells. Alternative, embodiments include a memory including a row of memory arrays, or a column of memory arrays, or multiple rows and multiple columns of memory arrays.

Abstract: Applying a bias voltage to unselected word-lines reduces program disturb of the threshold voltages of unselected memory cells during a write to a non-volatile memory. Applying the bias voltage only to memory cells which have already been written with threshold voltages higher than a minimum value and not to erased (or virgin) memory cells allows the bias voltage to be higher without creating currents through unselected memory cells. Data such as a series of samples representing a continuous analog signal can be recorded by writing to sequential addresses to fill one row in an array with data before writing to the next row. Bias flag circuits in a row decoder of the memory indicate which rows are filled with data and therefore which word-lines should have the bias voltage applied during a write.

Abstract: A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced. A real-time recording method in accordance with an embodiment of the invention writes digital samples to the memory using a fast digital write circuit while data is being acquired.

Abstract: A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read circuit process determines a memory cell's threshold voltage by slowly ramps the control gate voltage of a memory cell being read and senses when the memory cell conducts. Another read circuit determines the threshold voltage of a memory cell using a source follower read process and a ramping circuit which slowly increases the source voltage. Still another read circuit includes a cascoding device connectable to a memory cell, bias circuit for biasing the memory cell in its linear region, and a load which carries a current that mirrors the current through the memory cell wherein the threshold voltage of the memory cell is determined from a voltage across the load. Read circuits disclosed can be used with analog memory cells, binary memory cells, multi-level digital memory cells, and other applications which require precise reading of threshold voltages.

Abstract: A read circuit includes a driver which changes a gate voltage of a memory cell and a sense circuit which identifies when the memory cell trips. The driver searches for the threshold voltage of the memory cell using stages which ramp up gate voltage and stages which ramp down the gate voltage. Each stage ends when the sense circuit senses that the memory cell trips, i.e. begins or stops conducting. Initial stages of the search have high ramp rates so that the gate voltage reaches the threshold voltage. These initial stages can give inaccurate threshold voltage readings because high ramp rates change the gate voltage during the period between the transistor tripping and sensing the trip. Later stages ramp the gate voltage slowly to provide an accurate threshold voltage reading. The low ramp rate of the last stage provides accuracy, and the high ramp rate of the initial stages reduces read time. To further reduce read time, the search process can begin at a median voltage for possible threshold voltages.

Abstract: To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a node (source or drain) of the transistor. A reference voltage is asserted to a second input terminal of the differential amplifier. A load provides a current which charges the node, and the differential amplifier adjusts the gate voltage of the memory cell to an equilibrium value where current through the transistor is equal to current through the reference cell. The equilibrium value of the gate voltage depends on and indicates the threshold voltage of the transistor. In one embodiment of the invention, the load is a current source which mirrors a current through a reference cell that is structurally identical to the transistor, and the drain of the reference cell provides the reference voltage to the amplifier.

Abstract: A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced.