Abstract: Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

Abstract: Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 ? thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract: Methods of forming cobalt films utilizing a cobalt precursor comprising an additive are described. Those methods may include adding an additive to a cobalt precursor, wherein the cobalt precursor is located in an ampoule that is coupled with a deposition tool, and then forming a cobalt film using the cobalt precursor comprising the additive. Non-volatile decomposition products of the cobalt precursor are solubilized in the ampoule.

Abstract: The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element.

Abstract: Methods of forming cobalt films utilizing a cobalt precursor comprising an additive are described. Those methods may include adding an additive to a cobalt precursor, wherein the cobalt precursor is located in an ampoule that is coupled with a deposition tool, and then forming a cobalt film using the cobalt precursor comprising the additive. Non-volatile decomposition products of the cobalt precursor are solubilized in the ampoule.

Abstract: Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

Abstract: A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein the metal precursor is selected from the group consisting of (i) a Co2(CO)6(R1C?CR2), wherein R1 and R2 are individually selected from a straight or branched monovalent hydrocarbon group have one to six carbon atoms that may be interrupted and substituted; (ii) a mononuclear cobalt carbonyl nitrosyl; (iii) a cobalt carbonyl bonded to one of a boron, indium, germanium and tin moiety; (iv) a cobalt carbonyl bonded to a mononuclear or binuclear allyl; and (v) a cobalt (II) complex comprising nitrogen-based supporting ligands.

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (?)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract: An energy storage device comprises a first porous semiconducting structure (510) comprising a first plurality of channels (511) that contain a first electrolyte (514) and a second porous semiconducting structure (520) comprising a second plurality of channels (521) that contain a second electrolyte (524). In one embodiment, the energy storage device further comprises a film (535) on at least one of the first and second porous semiconducting structures, the film comprising a material capable of exhibiting reversible electron transfer reactions. In another embodiment, at least one of the first and second electrolytes contains a plurality of metal ions. In another embodiment, the first and second electrolytes, taken together, comprise a redox system.

Abstract: In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer. A separator separates the first and second nanostructured substrates and allows ions of an electrolyte to pass through the separator. The structure may be a nanostructured electrolytic capacitor with the first nanostructured substrate forming a positive electrode and the second nanostructured substrate forming a negative electrode of the capacitor.

Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages.

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.

Abstract: Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (?)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract: The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.