Abstract: A computing system can include at least one processing circuit that can monitor a first plurality of interactions with a plurality of Automated Teller Machines (ATMs), detect a change from a first status of a first ATM of the plurality of ATMs to a second status of the first ATM, retrieve information corresponding to a second plurality of interactions with the first ATM, identify one or more profiles associated with respective interactions of the second plurality of interactions, determine a plurality of user devices enrolled in a subscription to receive status updates regarding the first ATM, and transmit a signal to the plurality of user devices to cause the plurality of user devices to display a user interface to identify the second status of the first ATM.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for customizing personalization settings for a user. An example method includes receiving initiating event data and generating a first output. The example method further includes determining a target setting from the personalization settings and a target setting recommendation and generating a conversation prompt providing information about the target setting recommendation. The example method further includes presenting the conversation prompt to the user and receiving a user response. The example method further includes generating a second output and updating the target setting recommendation.

Abstract: Described herein are technologies for application authentication and/or data encryption without stored pre-shared keys. In one resource controller, a processing device receives an application identifier (ID) from the application. The processing device provides a current nonce responsive to the application ID and provides the application access to the system resource responsive to determining that a hash of a current key received from the application equals a current tag. The current key is generated by the application based on code of the application and the current nonce. The current tag was previously provided from the application to the resource controller. The current tag can also be hashed by the application using the current key.

Abstract: A first address bus may be located in an upper layer of an integrated circuit that is associated with a memory and a memory controller. The first address bus may receive a first portion of a memory address. A second address bus may be located in a lower layer of the integrated circuit where the second address bus is to receive a second portion of the memory address. Furthermore, a data bus may be located in an intermediate layer where the data bus is to receive data corresponding to the memory address from the memory and may transmit the data to the memory controller. The intermediate layer may be between the upper layer and the lower layer. A layout of the signals of the data bus may vertically overlap with a layout of signals of the first address bus and a layout of signals of the second address bus.

Abstract: A first address bus may be located in an upper layer of an integrated circuit that is associated with a memory and a memory controller. The first address bus may receive a first portion of a memory address. A second address bus may be located in a lower layer of the integrated circuit where the second address bus is to receive a second portion of the memory address. Furthermore, a data bus may be located in an intermediate layer where the data bus is to receive data corresponding to the memory address from the memory and may transmit the data to the memory controller. The intermediate layer may be between the upper layer and the lower layer. A layout of the signals of the data bus may vertically overlap with a layout of signals of the first address bus and a layout of signals of the second address bus.

Abstract: Described herein are technologies for application authentication and/or data encryption without stored pre-shared keys. In one resource controller, a processing device receives an application identifier (ID) from the application. The processing device provides a current nonce responsive to the application ID and provides the application access to the system resource responsive to determining that a hash of a current key received from the application equals a current tag. The current key is generated by the application based on code of the application and the current nonce. The current tag was previously provided from the application to the resource controller. The current tag can also be hashed by the application using the current key.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.

Abstract: This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.

Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.