Abstract: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Systems and methods are shown for reading data. One method includes receiving at a first circuit, from a second circuit, a plurality of data input signals and a timing reference signal, generating a plurality of oversampled data input signal and an oversampled timing reference signal, and determining a bit boundary range in the oversampled timing reference signal. The bit boundary range is then applied to the oversampled data input signals to determine a plurality of data words from the plurality of oversampled data input signals.

Abstract: An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.

Abstract: In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated with a low-retention row of storage cells once every nth refresh interval.

Abstract: A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.

Abstract: A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the type of termination selected, a capability for dynamic control of the termination impedance is provided. Moreover, an ability to change impedances of termination elements to maintain a desired termination impedance for both single-reference termination and center termination modes by shifting bits is provided. Also, a capability for dynamic control of transition times of signals is provided.

Abstract: A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the type of termination selected, a capability for dynamic control of the termination impedance is provided. Moreover, an ability to change impedances of termination elements to maintain a desired termination impedance for both single-reference termination and center termination modes by shifting bits is provided. Also, a capability for dynamic control of transition times of signals is provided.

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative to the electrical structure to develop an electrostatic aligning force between the charged alignment pads and their counterparts. When the integrated circuit die and electrical structure are enabled to move relative to one another, the electrostatic aligning force shifts the relative positioning of the integrated circuit die and electrical structure toward a desired alignment.

Abstract: Self-timed interfaces and methods are provided for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed interface couples the strobe signal to a receiver that samples data of data line under control of the strobe signal. A second signal path of the self-timed interface couples the strobe signal to an interface circuit through a hysteresis-based element. The interface circuit, under control of an output of the hysteresis-based element along with a clock signal that originates under a second clock domain, generates an interface enable signal for use in controlling data transfers between the different clock domains.

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a transmitter die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains the termination resistances for the signal transmission lines. The ODT control system derives a number of calibration currents from precision voltage and resistance references and distributes the reference currents to a number of transmitters. Each transmitter then derives an ODT calibration signal using the respective reference current and another precision resistor, and then employs the calibration signal to calibrate local termination elements. Distributing calibrated currents provides excellent noise immunity, while limiting the requisite number of external voltage references reduces cost.

Abstract: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Abstract: Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: A hybrid wireless and wired system distributes precise timing and synchronization information among the nodes over a wired interconnect structure while data is transmitted wirelessly using ultra-wideband radio over short distances. The timing information communicated over the wired interconnect structure is used to establish a baseline timing reference for the wireless transmitters, receivers and transceivers on the nodes of the communication network. Using a common timing reference, a mesochronous communication system is established for chip-to-chip wireless data transmission.

Abstract: A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures.

Abstract: A card assembly (20) having multiple layers for matching an article to a vehicle. The card assembly (20) includes a liner (28) having a first adhesive (36) and a first layer (40) along with a second adhesive (38) and a second layer (42). A scoreline (26, 50) extends through the first layer (40), first adhesive (36), and liner (28) to define a tag portion (24, 52) of the card assembly. The tag portion (24, 52) may be removed from the second adhesive (38) to expose a portion of the second adhesive (38), which defines an attachment area (48, 54) of a card portion (22). The card portion (22) may be adhered to a vehicle surface, such as the interior of a window, by the attachment area (48, 54). The removed tag portion (24, 52) may be attached to an article, such as a key set, for matching the article to the vehicle.