Abstract: Apparatus, systems, and method for efficiently cooling computing devices having heat-generating electronic components, such as, for example, independently operable servers, immersed in a dielectric liquid coolant in a tank.

Abstract: A computing system includes one or more rack rows comprising one or more racks. The racks includes one or more tanks that hold liquid coolant for at least one of the one or more servers, and a liquid coolant to remove heat from at least one of the one or more servers. An aisle is provided next to a rack row or between two of the rack rows. The aisle includes a floor. The floor can be walked on by service personnel to access at least one of the one or more racks in at least one of the rows. Cooling components at least partially below the aisle move a liquid to remove heat from at least one of the servers in at least one of the racks. The racks, floor and cooling components may be fire-resistant.

Abstract: A computing module includes one or more racks, one or more cooling components, and one or more power distribution components. The racks include one or more servers and one or more tanks that hold liquid coolant for the servers. The one or more cooling components move a liquid to remove heat from the servers. The one or more power distribution components supply power to the servers. The one or more racks, one or more cooling components, and one or more power distribution components are commonly coupled to one another to be movable as a unit.

Abstract: A node for performing computing operations includes a frame, a power supply coupled to the frame, and one or more liquid coolant-submersible motherboard assemblies. The one or more motherboard assemblies are configured to operate when submersed in a liquid coolant. The motherboard assemblies are mounted on the frame with one or more spaces between. The spaces form one or more channels between the motherboard assemblies. The frame includes an opening on at least one end of the one or more channels.

Abstract: Hard disk drives and computing systems to which they are connected are cooled by submerging the computing systems into a dielectric liquid coolant in a tank and by thermally coupling the hard disk drives to a heat conductive extension that is partly submerged into the coolant and partly out of the coolant. To keep the hard disks drives out of the coolant, they are mounted to the part of the heat conductive extension that is out of the coolant. In such a configuration, the hard disk drives are cooled through conduction of the heat from the hard disk drive to the coolant via the heat conductive extension. A pump may be used to move warmer coolant from the tank into a heat exchanger where the coolant is cooled and to move the cooled coolant back into the tank.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters.

Abstract: This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.

Abstract: Apparatus, systems, and methods for efficiently cooling computing devices having heat-generating electronic components, such as, for example, independently operable servers, immersed in a dielectric liquid coolant in a tank.

Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative to the electrical structure to develop an electrostatic aligning force between the charged alignment pads and their counterparts. When the integrated circuit die and electrical structure are enabled to move relative to one another, the electrostatic aligning force shifts the relative positioning of the integrated circuit die and electrical structure toward a desired alignment.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Methods and apparatuses for calibrating out static timing offsets across multiple outputs of a transmitting device are provided. In accordance with at least one embodiment, a signal is selected as the master reference signal, and a closed-loop feedback system is provided to align one or more outputs of the transmitting device to a master reference signal. The master reference signal can be one of the signals being output by the transmitting device, an internal signal that is representative of the desired placement of the edges, or an external signal received by the transmitting device. The signal from the transmitting device is received by a receiver, and a calibration control block is used to generate a control signal to adjust the operation of the transmitting device.

Abstract: In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter and a second AC-coupled transmitter. The first AC-coupled transmitter includes a first driver having a first input to receive first data and a first output. A first AC-coupling element couples the first output to a common output node. The second AC-coupled transmitter includes a second driver having a second input to receive second data, and a second output. A second AC-coupling element couples the second output to the same first common output node.