Patents by Inventor Scott E. Smith
Scott E. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12189414Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.Type: GrantFiled: August 29, 2022Date of Patent: January 7, 2025Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, Navya Sri Sreeram, Scott E. Smith
-
Publication number: 20240420746Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.Type: ApplicationFiled: August 26, 2024Publication date: December 19, 2024Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
-
Patent number: 12165690Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.Type: GrantFiled: June 24, 2022Date of Patent: December 10, 2024Assignee: Micron Technology, Inc.Inventors: John E. Riley, Joo-Sang Lee, Scott E. Smith
-
Publication number: 20240395311Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Noriaki Mochida, Takayuki Miyamoto, Kallol Mazumder, Scott E. Smith
-
Patent number: 12087394Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.Type: GrantFiled: September 8, 2022Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
-
Publication number: 20240281327Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, both the metadata and the data may be provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.Type: ApplicationFiled: February 14, 2024Publication date: August 22, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Patent number: 12068021Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.Type: GrantFiled: May 17, 2022Date of Patent: August 20, 2024Assignee: Micron Technology, Inc.Inventors: Noriaki Mochida, Takayuki Miyamoto, Kallol Mazumder, Scott E. Smith
-
Publication number: 20240176699Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an ×4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.Type: ApplicationFiled: November 8, 2023Publication date: May 30, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Publication number: 20240170088Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.Type: ApplicationFiled: November 8, 2023Publication date: May 23, 2024Applicant: Micron Technology, Inc.Inventors: Scott E. Smith, Sujeet Ayyapureddi
-
Publication number: 20240160351Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Publication number: 20240161856Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Scott E. Smith, Sujeet Ayyapureddi
-
Publication number: 20240160527Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Publication number: 20240161855Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Scott E. Smith, Sujeet Ayyapureddi
-
Publication number: 20240161809Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.Type: ApplicationFiled: January 18, 2024Publication date: May 16, 2024Inventors: Miles S. Wiscombe, Scott E. Smith, Gary L. Howe, Brian W. Huber, Tony M. Brewer
-
Publication number: 20240160524Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Publication number: 20240161859Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Scott E. Smith
-
Publication number: 20240087621Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
-
Publication number: 20240078153Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.Type: ApplicationFiled: May 8, 2023Publication date: March 7, 2024Inventors: Aaron Jannusch, Brett K. Dodds, Debra M. Bell, Joshua E. Alzheimer, Scott E. Smith
-
Publication number: 20240069589Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Inventors: Kallol Mazumder, Navya Sri Sreeram, Scott E. Smith
-
Patent number: 11908509Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.Type: GrantFiled: March 23, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: John E. Riley, Scott E. Smith, Jennifer E. Taylor, Gary L. Howe