Abstract: A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Abstract: The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

Abstract: The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be utilized to ground the internal voltage buses. With the internal voltage buses grounded, the outputs of the level shifters, which are control signals, may need to be forced into specific states. Through the use of the grounding devices and level shifters, leakage may be reduced and latch-up conditions may be reduced. As a result, the operation of the semiconductor chip may be enhanced because the problems associated with grounding the internal voltage buses may be diminished.

Abstract: The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.

Abstract: A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).

Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).

Abstract: A circuit is designed with a detector circuit (700) coupled between a supply voltage terminal (705) and a reference voltage terminal (755). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (205, 207) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (215) in response to the first and third control signals. A second circuit (203) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.

Abstract: A bandgap reference circuit (10) with improved startup circuitry is disclosed. The bandgap reference circuit (10) includes a startup node (NBIAS) that is connected to the gates of n-channel MOS transistors (38n, 39n) in first and second conduction legs of a current mirror. A series of inverters (51, 53, 55) turn on a transistor (50) that is connected between a precharge node (TO) and the startup node (NBIAS) in response to a signal (RID) indicating recent power-up of a power supply voltage (Vdd). A capacitor (60) is also provided, and which is discharged upon power-down. The capacitor (60) is connected to the gate of a p-channel transistor (70) that has its source/drain path connected between the precharge node (TO) and the startup node (NBIAS), and that is turned on upon power-up, even if the power-up signal (RID) is not generated, thus ensuring initiation of the bandgap reference circuit (10).

Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Abstract: An integrated circuit includes a voltage supply internal to the integrated circuit and circuitry for sensing the voltage level of the internal voltage supply, the circuitry responsive to produce a flag signal, VPUEN, that is in a first logical state when the voltage level is below the desired level and in a second logical state when the voltage level is above the desired level. The integrated circuit also includes a buffer driver 406 having an input terminal and an output terminal, the input terminal being coupled to the circuitry for sensing the voltage level of the internal voltage supply. The operation of the circuit is such that the output terminal 400 of the buffer driver is in a high-impedance state when the flag signal is in the first logical state, and is responsive to data signals on the input terminal to produce corresponding output signals at the output terminal when the flag signal is in the second logical state.

Abstract: A vapor permeable pressurized package is disclosed. The package includes a container defining an interior space and a partition dividing the interior space of the container into a first compartment for storing a product to be dispensed from the container and a second compartment for storing a propellant employed to selectively force the product through the outlet of the container. The partition includes pores selectively permitting propellent vapor to pass from the second compartment to the first compartment. The propellant vapor stored in the second compartment moves into the first compartment when the container is actuated for the release of the product stored in the first compartment, causing the product to be expelled through the outlet of the container.