Abstract: A vapor permeable pressurized package is disclosed. The package includes a container defining an interior space and a partition dividing the interior space of the container into a first compartment for storing a product to be dispensed from the container and a second compartment for storing a propellant employed to selectively force the product through the outlet of the container. The partition includes pores selectively permitting propellent vapor to pass from the second compartment to the first compartment. The propellant vapor stored in the second compartment moves into the first compartment when the container is actuated for the release of the product stored in the first compartment, causing the product to be expelled through the outlet of the container.

Abstract: A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).

Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Abstract: A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Abstract: The present invention relates to improved product dispensers for various products, including solids, gels, semi-solids, and other substantially solid products. In a preferred embodiment of the present invention, the dispenser is in the form of an improved twist-up type dispenser with an application/distribution surface in the form of a mesh applicator head for covering the exposed end of a solid stick of product. The dispenser includes a force-limiting mechanism to limit the force exerted by the product on the mesh applicator head during pre-loading to prevent extrusion of the product. The dispenser further includes a force-maintaining mechanism to maintain the surface of the product in continuous intimate contact with the mesh applicator head during the application process. The surface of the product exposed via the apertures is sheared off in conventional fashion, and the mesh provides for a more even distribution of the product than conventional solid stick-type dispensers.

Abstract: A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

Abstract: An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

Abstract: An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.

Abstract: Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.

Abstract: The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements.

Abstract: Improved transdermal drug delivery systems are provided which contain an occlusive, elastomeric backing layer which is preferably liquid-resistant. The systems contain as a backing layer a single homogeneous sheet of an elastomeric material having a moisture vapor transmission rate ("MVTR") in the range of about 0.1 to 20 g/m.sup.2 /hr and a Young's modulus in the range of about 10.sup.4 to 10.sup.9 dynes/cm.sup.2. Methods for making and using transdermal drug delivery devices containing such backing layers are provided as well.

Abstract: Antiperspirant aerosol compositions comprising from about 1% to about 40% of a particulate antiperspirant material, from about 0.005% to about 6.0% of a functionalized siloxane and from about 60% to about 95% of an aerosol propellant. Preferably the functionalized siloxane is an amino-functional silicone. Also preferably, the compositions also contain a silicon gum material and a volatile silicone oil.