Patents by Inventor Scott J. Derner

Scott J. Derner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Half density ferroelectric memory and operation
    Patent number: 10360966
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Ferroelectric memory cells
    Patent number: 10354712
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Apparatuses comprising memory cells, and apparatuses comprising memory arrays
    Patent number: 10347635
    Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Michael Amiel Shore, Charles L. Ingalls, Steve V. Cole
  • Sense amplifier constructions
    Patent number: 10339985
    Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner
  • SYSTEM, APPARATUS, AND RELATED METHOD FOR GENERATING A GEOSPATIAL INTERACTIVE COMPOSITE WEB-BASED IMAGE MAP
    Publication number: 20190163349
    Abstract: A system, apparatuses such as a non-transitory readable medium, and a method for generating a geospatial interactive composite web-based image map are disclosed. The system may be configured to receive, from a user device, a request for creating a geospatial interactive composite web-based image map for a selected region of map data displayed by the user device, select images responsive to the request corresponding to defined sub-regions within the selected region of the map data displayed by the user device, construct a collage for the geospatial composite web-based image map responsive to selecting the images, and transmit the collage to the user device for display thereon as an overlay to the map data.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 30, 2019
    Inventors: Scott J. Derner, Patrick Mullarkey
  • Memory arrays
    Patent number: 10276230
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Memory Cells and Memory Arrays
    Publication number: 20190096894
    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Debra M. Bell, Scott J. Derner
  • Memory Cells and Memory Arrays
    Publication number: 20190088652
    Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Memory Cells and Memory Arrays
    Publication number: 20190088653
    Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Michael Amiel Shore
  • Memory Arrays
    Publication number: 20190049087
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Application
    Filed: September 21, 2018
    Publication date: February 14, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • APPARATUSES AND METHODS FOR MEMORY INCLUDING FERROELECTRIC MEMORY CELLS AND DIELECTRIC MEMORY CELLS
    Publication number: 20190019553
    Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.
    Type: Application
    Filed: June 11, 2018
    Publication date: January 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Michael A. Shore
  • Memory Circuitry
    Publication number: 20190019544
    Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls, Tae H. Kim
  • APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY
    Publication number: 20190013057
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and, for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Application
    Filed: September 14, 2018
    Publication date: January 10, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Memory cells and memory arrays
    Patent number: 10177159
    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Scott J. Derner
  • FERROELECTRIC MEMORY CELLS
    Publication number: 20190005999
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Application
    Filed: August 17, 2018
    Publication date: January 3, 2019
    Inventors: SCOTT J. DERNER, CHRISTOPHER J. KAWAMURA
  • Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays
    Publication number: 20190006365
    Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.
    Type: Application
    Filed: May 22, 2018
    Publication date: January 3, 2019
    Applicant: Micron Technology , Inc.
    Inventors: Scott J. Derner, Michael Amiel Shore, Charles L. Ingalls, Steve V. Cole
  • APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR OPERATING FERROELECTRIC MEMORY
    Publication number: 20180374528
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 27, 2018
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Memory cells and memory arrays
    Patent number: 10157926
    Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • SYSTEMS AND METHODS FOR MEMORY CELL ARRAY INITIALIZATION
    Publication number: 20180358084
    Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Scott J. Derner, HUY T. VO, PATRICK MULLARKEY, JEFFREY P. WRIGHT, MICHAEL A. SHORE
  • APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME
    Publication number: 20180358083
    Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Christopher J. Kawamura, Scott J. Derner