Patents by Inventor Scott J. Derner
Scott J. Derner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6934173Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: June 28, 2001Date of Patent: August 23, 2005Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6859408Abstract: Method and apparatus for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.Type: GrantFiled: August 29, 2002Date of Patent: February 22, 2005Assignee: Micron Technology, Inc.Inventors: Stephen R. Porter, Scott J. Derner
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Patent number: 6834022Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.Type: GrantFiled: November 18, 2003Date of Patent: December 21, 2004Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6816425Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: February 11, 2004Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20040158690Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: February 11, 2004Publication date: August 12, 2004Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20040125634Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: August 22, 2001Publication date: July 1, 2004Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6750700Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: July 13, 2001Date of Patent: June 15, 2004Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Publication number: 20040100847Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 18, 2003Publication date: May 27, 2004Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6724238Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antiftise circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: GrantFiled: May 29, 2003Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth
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Patent number: 6717873Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: December 12, 2002Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Patent number: 6710631Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: July 20, 2001Date of Patent: March 23, 2004Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Publication number: 20040042318Abstract: Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Stephen R. Porter, Scott J. Derner
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Patent number: 6696867Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: July 18, 2001Date of Patent: February 24, 2004Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6686786Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: June 25, 2001Date of Patent: February 3, 2004Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6678186Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other.Type: GrantFiled: August 12, 2002Date of Patent: January 13, 2004Assignee: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Scott J. Derner
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Patent number: 6674310Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: August 15, 2001Date of Patent: January 6, 2004Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Publication number: 20030234679Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: ApplicationFiled: May 29, 2003Publication date: December 25, 2003Inventors: Scott J. Derner, Casey R. Kurth
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Patent number: 6650587Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: GrantFiled: November 19, 2001Date of Patent: November 18, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6611165Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: GrantFiled: June 25, 2002Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth
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Patent number: 6597206Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mix, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: August 1, 2001Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner