Patents by Inventor Scott J. Derner
Scott J. Derner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030122587Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: July 20, 2001Publication date: July 3, 2003Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6580631Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: August 8, 2001Date of Patent: June 17, 2003Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Publication number: 20030095459Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 19, 2001Publication date: May 22, 2003Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Publication number: 20030081476Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: December 12, 2002Publication date: May 1, 2003Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Patent number: 6556467Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.Type: GrantFiled: August 29, 2001Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Scot M. Graham
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Patent number: 6556065Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: July 21, 2000Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6525958Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.Type: GrantFiled: October 23, 2001Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventor: Scott J. Derner
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Patent number: 6519190Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.Type: GrantFiled: October 23, 2001Date of Patent: February 11, 2003Assignee: Micron Technology, Inc.Inventor: Scott J. Derner
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Patent number: 6515915Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.Type: GrantFiled: October 23, 2001Date of Patent: February 4, 2003Assignee: Micron Technology, Inc.Inventor: Scott J. Derner
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Patent number: 6515925Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: March 15, 2001Date of Patent: February 4, 2003Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20030021138Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: August 22, 2001Publication date: January 30, 2003Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Publication number: 20020191463Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other.Type: ApplicationFiled: August 12, 2002Publication date: December 19, 2002Applicant: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Scott J. Derner
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Publication number: 20020149957Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: July 10, 2001Publication date: October 17, 2002Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner, Ronald L. Taylor, John S. Mullin, Raymond J. Beffa, Frank F. Ross, Larry D. Kinsman
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Publication number: 20020131311Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20020118585Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.Type: ApplicationFiled: August 29, 2001Publication date: August 29, 2002Inventors: Scott J. Derner, Scott M. Graham
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Patent number: 6434072Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires.Type: GrantFiled: May 22, 2001Date of Patent: August 13, 2002Assignee: Micron TechnologyInventors: Patrick J. Mullarkey, Scott J. Derner
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Publication number: 20020089880Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.Type: ApplicationFiled: October 23, 2001Publication date: July 11, 2002Applicant: Micron Technology, Inc.Inventor: Scott J. Derner
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Publication number: 20020080671Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.Type: ApplicationFiled: October 23, 2001Publication date: June 27, 2002Applicant: Micron Technology, Inc.Inventor: Scott J. Derner
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Publication number: 20020080639Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: August 31, 2001Publication date: June 27, 2002Inventors: Brent Keeth, Layne G. Bunker, Scott J. Derner
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Patent number: 6410385Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.Type: GrantFiled: April 13, 2001Date of Patent: June 25, 2002Assignee: Micron Technology, Inc.Inventors: Casey R. Kurth, Scott J. Derner, Patrick J. Mullarkey