Patents by Inventor Scott Robert Summerfelt
Scott Robert Summerfelt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190339806Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Wei-Yan Shih, Steve Kummerl, Mark Stephen Toth, Alok Lohia, Terry Lee Sculley, Seung Bae Lee, Scott Robert Summerfelt
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Patent number: 10353503Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.Type: GrantFiled: October 29, 2015Date of Patent: July 16, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wei-Yan Shih, Steve Kummerl, Mark Stephen Toth, Alok Lohia, Terry Lee Sculley, Seung Bae Lee, Scott Robert Summerfelt
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Publication number: 20190051812Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.Type: ApplicationFiled: August 8, 2017Publication date: February 14, 2019Inventors: Wei-Yan Shih, Sudhanshu Khanna, Michael Zwerg, Juergen Luebbe, Gregory Allen North, Steven C. Bartling, Leah Trautmann, Scott Robert Summerfelt
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Publication number: 20180374861Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: August 7, 2018Publication date: December 27, 2018Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillemo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Publication number: 20170123548Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.Type: ApplicationFiled: October 29, 2015Publication date: May 4, 2017Inventors: Wei-Yan Shih, Steve Kummerl, Mark Stephen Toth, Alok Lohia, Terry Lee Sculley, Seung Bae Lee, Scott Robert Summerfelt
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Publication number: 20160086960Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: June 2, 2015Publication date: March 24, 2016Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Publication number: 20150221516Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.Type: ApplicationFiled: April 9, 2015Publication date: August 6, 2015Inventors: Mark Robert Visokay, Scott Robert Summerfelt
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Patent number: 9070575Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: GrantFiled: July 29, 2013Date of Patent: June 30, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Patent number: 9035458Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.Type: GrantFiled: January 20, 2014Date of Patent: May 19, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
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Patent number: 8753952Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: GrantFiled: December 20, 2011Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Publication number: 20140147940Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.Type: ApplicationFiled: November 25, 2013Publication date: May 29, 2014Applicant: Texas Instruments IncorporatedInventors: Mark Robert Visokay, Scott Robert Summerfelt
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Publication number: 20140131781Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.Type: ApplicationFiled: January 20, 2014Publication date: May 15, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
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Patent number: 8652855Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.Type: GrantFiled: March 29, 2012Date of Patent: February 18, 2014Assignee: Texas Instruments IncorporatedInventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
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Publication number: 20130313679Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Inventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Publication number: 20130082314Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.Type: ApplicationFiled: March 29, 2012Publication date: April 4, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
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Publication number: 20130062733Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: ApplicationFiled: December 20, 2011Publication date: March 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Patent number: 7985603Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: GrantFiled: February 4, 2008Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Patent number: 7723199Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: GrantFiled: January 31, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Publication number: 20090194801Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Applicant: Texas Instruments Inc.Inventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Publication number: 20070298521Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: ApplicationFiled: January 31, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise