METHOD OF FABRICATING ULTRA THIN FLIP-CHIP PACKAGE

Abstract

Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film. each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 10/973,528, filed Oct. 25, 2004, now pending, which is claims priority from Korean Patent Application No. 2003-74660, filed on Oct. 24, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This disclosure relates to a method of fabricating a semiconductor package, and more particularly, to a method of fabricating an ultra thin flip-chip package.

2. Description of the Related Art

To mount a semiconductor chip on a printed circuit board (PCB), flip-chip packaging can be used. Flip-chip packaging is a method of directly bonding a bond pad of a semiconductor chip to a PCB, and has advantages of occupying a small area and a fast operating speed.

FIGS. 1 through 8 are sectional views illustrating a conventional method of fabricating a flip-chip package.

Referring to FIG. 1, a semiconductor chip 17 including a bond pad 13 formed on a semiconductor substrate 11 and a passivation film pattern 15 partially exposing the bond pad 13 is prepared. A polyimide film pattern 19 exposing an upper surface of the bond pad 13 is formed on the passivation film pattern 15. The polyimide film pattern 19 protects the surface of the semiconductor chip 17.

A first under barrier metal film 21 is formed on the semiconductor chip 17 and the polyimide film pattern 19. Accordingly, a portion of the first under barrier metal film 21 is formed on the bond pad 13. The first under barrier metal film 21 is a composite film including a titanium film and a nickel film stacked sequentially.

Referring to FIG. 2, by forming a photoresist film on the first under barrier metal film 21 and patterning the photoresist film, a photoresist pattern 23 having a hole 22 exposing a region above the bond pad 13 is formed. The first under barrier metal film 21 on the bond pad 13 is exposed by the photoresist pattern 23.

Next, referring to FIG. 3, a second under barrier metal film 25 is then formed on the exposed portion of the first under barrier metal film 21. The second under barrier metal film 25 is formed by an electroplating method in which the photoresist pattern 23 is used as an electroplating-preventing film. The second under barrier metal film 25 is a nickel film.

Referring to FIG. 4, a solder bump 27 is formed on the second under barrier metal film 25 so as to fill the hole 22 of the photoresist pattern 23. The solder bump 27 is formed by an electroplating method in which the photoresist pattern 23 is used as a film for preventing an electroplating, The solder bump 27 is formed of an alloy film composed of lead and tin.

Referring to FIG. 5, the photoresist pattern 23 is removed. Then, referring to FIG. 6, the first under barrier metal film 21 is etched by using the solder bump as an etch mask. Accordingly, the first under barrier metal film 21 is disposed only below the second under barrier metal film 25.

Referring to FIGS. 7 and 8, a water-soluble flux 29 is coated on the resultant structure to cover the solder bump 27. Thereafter, the solder bump 27 is reflowed by a thermal process using the water-soluble flux 29, and is made in a rounded form. Then, although not shown in the drawings, the semiconductor chip 17 on which the solder bump 27 is formed is directly bonded to a PCB (not shown), thereby completing the fabrication of the flip-chip package.

The method of fabricating the flip-chip package in FIGS. 1 through 8 has the following drawbacks.

First, in the conventional method, the height of the solder bump 27 should be limited to a height of 100 μm so as to permit the packaging of the semiconductor chip. Due to this limitation, it is difficult to realize an ultra thin flip-chip package. Also, when the solder bump is made to the height of 100 μm, the height of the photoresist pattern used as the electroplating-preventing film should be at least 70 μm, which results in an increase in the fabrication costs.

Secondly, in the conventional method, since the increase in the integrity of a semiconductor chip requires the size of the bond pad and the height of the solder bump to be decreased, the structural reliability of the flip-chip package is lowered.

Thirdly, in the conventional method, since a joint crack generated in the solder layer is propagated after the bonding of the solder bump and the PCB, the structural reliability of the flip-chip package is lowered.

Fourthly, since the conventional method requires the complicated processes as illustrated in FIGS. 1 through 8, especially the reflow process of the solder bump, the flip-chip package is subject to thermal stress.

SUMMARY OF THE INVENTION

Embodiments of the invention provide methods of fabricating an ultra thin flip-chip package, capable of reducing fabrication costs and enhancing the structural reliability by using a simplified process.

In one embodiment, a semiconductor package comprises a semiconductor chip including a bond pad formed on a semiconductor substrate and a passivation film pattern overlying the semiconductor substrate and exposing the bond pad. A first under barrier metal film is formed on the bond pad. A plurality of solder bumps are formed overlying the first under barrier metal film. The solder bumps each include a bar portion and a ball portion formed at an end of the bar portion. The package further includes a package substrate such as a printed circuit board. The ball portions of the solder bumps are contacted with the package substrate to form a semiconductor package.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIGS. 1 through 8 are sectional views illustrating a conventional method of fabricating a flip-chip package.

FIGS. 9 through 17 are sectional views illustrating a method of fabricating an ultra thin flip-chip package according to an embodiment of the invention.

FIG. 18 is a plan view of solder bumps made when the ultra thin flip-chip is fabricated according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will now be described more fully with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity.

FIGS. 9 through 17 are sectional view illustrating a method of fabricating an ultra thin flip-chip package according to an embodiment of the invention, and FIG. 18 is a plan view of solder bumps made when the ultra thin flip-chip is fabricated according to an embodiment of the invention.

Referring to FIG. 9, a semiconductor chip 107 including a bond pad 103 and a passivation film pattern 105 exposing the bond pad 103 formed on a semiconductor substrate 101 is prepared. The bond pad 103 corresponds to an electrical connection passage of the semiconductor chip 107 to which an external electrical signal is applied. The bond pad 103 may be formed of an aluminum (Al) film or a copper (Cu) film. The passivation film pattern 105 is a material film protecting the semiconductor substrate 101 from contaminant particles or physical stress, and may be formed of a silicon nitride film.

On the passivation film pattern 105, a buffer film pattern 109 is formed. The buffer film pattern 109 is a material film that can reduces physical stress applied to the semiconductor chip 107 during the bonding of the semiconductor chip 107 to a printed circuit board (PCB). The buffer film pattern may be formed of a polyimide film.

Referring to FIG. 10, a first under barrier metal (UBM) film 111 is formed on the buffer film pattern 109 and the bond pad 103. The first under barrier metal film 111 increases an electrical conductive area of the bond pad 103. The first under barrier metal film 111 may be formed by a sputtering method, and may be a composite film including a titanium film and a nickel film, which are stacked sequentially.

Next, a photoresist film is coated on the first under barrier metal film 111 and is patterned to form a first photoresist pattern 113 having a hole 112 exposing a region of the first under barrier metal film 111 on the bond pad 103.

Referring to FIG. 11, a second under barrier metal (UBM) film 115 is formed on the exposed region of the first under barrier metal film 111. In other words, the second under barrier metal film 115 is formed on the first under barrier metal film 111 inside the hole 112. The second under barrier metal film 115 prevents the first under barrier metal film 111 from being diffused. The second under barrier metal film 115 may be formed by an electroplating method in which the photoresist pattern 113 is used as a film for preventing electroplating. The second under barrier metal film 115 may be formed of a gold (Au) film.

Next, referring to FIG. 12, the first photoresist pattern 113 is removed.

Referring to FIG. 13, a second photoresist pattern 117 is formed on the second under barrier metal film 115 and the first under barrier metal film 11. The second photoresist pattern 117 formed on the second tinder barrier metal includes a plurality of bars 116 with a plurality of holes 118 formed between the bars 16.

Referring to FIG. 14, a plurality of solder bumps 119 are formed on the second under barrier metal film 115 and fill the holes 118 through the second photoresist pattern 117. Each of the solder bumps 119 includes a bar portion 119a and a ball portion 119b formed at an upper portion of the solder bump 119. The ball portions 119b are bonded to each other to reduce the volume during a subsequent soldering process with a PCB. The solder bumps 119 may be formed by an electroplating method using the second photoresist pattern 117 as an electroplating-preventing film. The solder bumps 119 may be formed of an alloy film including lead and tin.

Referring to FIG. 15, the photoresist pattern 117 is removed. By doing so, formation of the three-dimensional structured solder bumps 119, including the bars 119a and the ball portions 119b, is completed.

Thus, although the three-dimensional structured solder bumps 119 are not as high as those of the prior art, a subsequent flip-chip bonding process can be easily performed, so that an ultra thin flip-chip package can be realized and the fabrication costs can be lowered.

The three-dimensional structured solder bumps are bonded to adjacent another solder bumps 119, particularly ball portions 119b, as shown in FIG. 18. Accordingly, the three-dimensional structured solder bumps 119 can secure a predetermined amount of solder volume, so that a super ultra thin flip-chip package can be realized.

Referring to FIG. 15, the first under barrier metal film 111 is etched using the second under barrier metal film 115 and the solder bumps 119 as an etch mask. Accordingly, the first under barrier metal film 111 is disposed only below the second under barrier metal film 115.

Referring to FIGS. 16 and 17, the semiconductor chip 107 including the solder bumps 119 may be bonded to a PCB 201 using a flux 203 by a soldering process, thereby completing a flip-chip package. The flip-chip package can prevent ajoint crack generated in the solder layer after the soldering process from propagating in a horizontal direction (direction perpendicular to the lengths of the bar of the solder bumps 119), and can also prevent the joint crack from propagating in a vertical direction (direction parallel to the lengths of the bars 119a of the solder bumps 119) due to the bars 119a of the solder bumps 119.

As described above, the method of fabricating an ultra thin flip-chip package according to an embodiment of the invention enables the realization of an ultra thin flip-chip package having enhanced structural reliability by employing three-dimensional structured solder bumps to decrease the heights of the solder bumps.

Also, a joint crack can be prevented from being propagated in the horizontal and vertical directions inside the solder layer because each of the solder bumps includes a bar with a ball portion at on end.

Further, since a flip-chip package can be realized with a simplified process compared to the conventional processes, and can omit the reflow process of the solder bumps, a flip-chip package not having thermal stress can be obtained.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A flip-chip package comprising:

a semiconductor chip including a bond pad formed on a semiconductor substrate and a passivation film pattern overlying the semiconductor substrate and exposing the bond pad;

a first under barrier metal film disposed on the bond pad;

a second under barrier metal film disposed on the first under barrier metal film;

a plurality of solder bumps disposed on the second under barrier metal film, each of the solder bumps including a bar portion and a ball portion formed at an end of the bar portion; and

a package substrate, wherein the bar portion of the solder bumps directly contacts the package substrate.

2. The package of claim 1, wherein the first under barrier metal film is formed of a composite film including a titanium film and a nickel film stacked sequentially.

3. The package of claim 1, wherein the solder bumps are formed of an alloy film including lead and tin.

4. The package of claim 1, wherein the second under barrier metal film is a nickel film.